2. Proposed flip-flop based timing-skew calibration logic
As mentioned in Introduction, in the proposed calibration method, the timing skew
between the sampling clocks are removed after comparing the timings of the sampling
clocks with that of the reference clock at the input of sub-ADCs. Fig. 3 shows the proposed skew calibration system. Each channel clocks generated by the
clock generator is supplied to a sub-ADC after passing through a variable delay line
(VDL). A skew detection circuit detects the polarity of the relative timing of a channel
clock ${\Phi}$$_{\mathrm{1\sim 4}}$ to that of the reference clock ${\Phi}$$_{\mathrm{REF}}$,
which is a copy of the 4-GHz input clock. The digital output of the skew detector
is delivered to a counter which controls the delay of the VDL. The timing skew of
the channel clocks is not expected to be very large, but it should be fine-tuned.
Therefore, VDLs for the channel clocks have 7-bit resolution (binary coded) with step
sizes of about 300 fs resulting in total ranges of about 38~ps.
The delay of ${\Phi}$REF itself is controlled by a coarse VDL of which the step-size
is much larger than that of the VDLs for the channel clocks. The purpose of the VDL
for ${\Phi}$$_{\mathrm{REF}}$ is to place the timing of ${\Phi}$$_{\mathrm{REF}}$
in the middle of the timings of the channel clocks. Whereas the channel clocks are
generated by CML clock dividers, the reference clock ${\Phi}$$_{\mathrm{REF}}$ is
produced by a simple chain of inverters. Therefore, depending on the PVT condition,
there can be relatively large relative delays between the reference and the channel
clocks, which should be compensated by a VDL. The resolution and the step size of
the coarse VDL are 3 bits and 30 ps, respectively, resulting in the total coverage
of about 200 ps, which is nearly one clock period of the target TI-ADC. We call the
VDL for ${\Phi}$$_{\mathrm{REF}}$ functions a coarse VDL and those for channel clocks
find VDLs.
The calibration logic flow is shown in Fig. 4. The 7-bit digital codes controlling the channel clock VDLs are updated in the direction
determined by the skew-polarity detectors which determine the polarity of the skew
of each channel clock against ${\Phi}$$_{\mathrm{REF}}$. A code reaching an end (i.e.,
0000000(2) or 1111111(2)) means that the corresponding channel clock VDL is out of
range. If any of the four channel-clock VDLs reaches an end, the delay of the reference
clock VDL is changed by one step, and the skew calibration for each channel is repeated
with the new coarse delay. Note that step sizes of the reference clock VDL is much
larger than the step size of the channel clock VDLs.
The calibration method proposed in this paper relies on our ability to determine the
relative timings of the channel clocks to that of ${\Phi}$$_{\mathrm{REF}}$. Therefore,
the design of skew detectors is at the core of our work. In this work, we used very
simple skew-polarity detectors consisting of mainly two D-flip flops (DFFs). The schematic
of the detector is shown in Fig. 5. Note that while Fig. 5 shows the signal connections of the detector which compares the timing of the second
channel clock ${\Phi}$$_{2}$ with that of ${\Phi}$$_{\mathrm{REF}}$, similar detectors
exist for other channels.
In Fig. 5, ${\Phi}$$_{\mathrm{REF}}$ or ${\Phi}$$_{2}$ are applied to the clock inputs of the
DFFs, and HI is applied to D inputs of both DFFs. The output of the DFF to which the
clock arrives earlier will become HI first. This HI output resets the opposite DFF
and prevents it from becoming HI when a clock arrives at the DFF later. Therefore,
the two interconnected flip-flops store the polarity of the timing skew. For example,
if a$_{2}$ = LO and b$_{2}$ = HI, it means that ${\Phi}$$_{2}$ is ahead of ${\Phi}$$_{\mathrm{REF}}$.
On the other hand, if a$_{2}$ = HI and b$_{2}$ = LO, it indicates the opposite case.
The timing skew must be re-evaluated regularly. To prepare the detector for a new
acquisition, the DFFs are reset when ${\Phi}$$_{1}$= HI, which is before the arrival
of a new ${\Phi}$$_{2}$. When ${\Phi}$$_{1}$ becomes LO again, the reset input of
DFFs are connected to the output of the opposite DFF again and the skew detector is
ready to accept new clock inputs. The output of the skew detector is accumulated by
a counter, of which the output controls a channel clock VDL.
Fig. 6 shows the waveform obtained from spice-level simulations using Spectre. We observe
very clean waveforms. Although x$_{2}$ rises a little when ${\Phi}$$_{\mathrm{REF}}$
arrives, it is soon reset by y$_{2}$. y$_{2}$ itself is reset by CK1.
When the skew is very small, it is possible that neither a$_{2}$ nor b$_{2}$ can fully
rise to HI because of their mutual reset operations. If that happens, it can lead
to malfunction of the calibration logic. To prevent this, a ‘forced decision’ circuit
is used. If none of the output of both DFFs becomes HI by the time ${\Phi}$$_{3}$
arrives, the FD flag is set, which forces a$_{2}$= HI and b$_{2}$= LO until next ${\Phi}$$_{1}$arrives.
The input range in which this forced decision occurs corresponds to a kind of ``dead-zone'',
which can limit the ultimate resolution of the skew detection. The width of the dead-zone
was estimated to be about 60 fs using simulations. Because it is very small, the forced
decision should not affect the calibration performance.
Fig. 7 shows the waveforms corresponding to this ‘forced decision’. Because of the proximity
of the arrival of ${\Phi}$$_{\mathrm{REF}}$ and ${\Phi}$$_{2}$, x2 and y2 reset each
other resulting in none of them reaching HI by the time CK3 arrives. Then, FD becomes
HI and a2 = HI and b2 = LO are produced.
Fig. 8 illustrates an example of the time evolution of the output of the skew-polarity detector
and the output of the counter D$_{2}$<6:0> applied to the channel clock VDL which
adjusts the timing of the channel clock ${\Phi}$$_{2}$. Fig. 8(a) represents the signal evolution before the calibration is completed. In this case,
${\Phi}$$_{2}$is leading ${\Phi}$$_{\mathrm{REF}}$. Therefore, a$_{2}$= LO and b$_{2}$=
HI are produced after each detection, which leads to a gradual increase of D$_{2}$<6:0>,
which, in turn, reduces the timing difference between ${\Phi}$$_{2}$ and ${\Phi}$$_{\mathrm{REF}}$.
Fig. 8(b) shows the signals after the calibration is completed. At this time, the a$_{2}$ and
b$_{2}$ toggles between HI and LO.
An example of the time evolution of the digital codes controlling ${\Phi}$$_{\mathrm{REF}}$
and ${\Phi}$$_{2}$ is illustrated in Fig. 9. It shows what happens when the counter for a channel clock reaches an end during
skew calibration. Here, at the beginning ${\Phi}$$_{2}$leads ${\Phi}$$_{\mathrm{REF}}$
and the code for ${\Phi}$$_{2}$is gradually increased until it reaches 1111111$_{\mathrm{(2)}}$.
Then, the code for ${\Phi}$REF is reduced by one bit. In this particular example,
the reduction by one bit of the code for ${\Phi}$REF is enough to make ${\Phi}$$_{\mathrm{REF}}$
leads ${\Phi}$$_{2}$. Therefore, the code for ${\Phi}$$_{2}$now begins to come down
until it toggles between two values. If a one-bit reduction of the code is not enough
to make ${\Phi}$$_{\mathrm{REF}}$ lead ${\Phi}$$_{2}$, then ${\Phi}$$_{\mathrm{REF}}$
is reduced repeatedly until it leads ${\Phi}$$_{2}$.
If there is a mismatch between the clock-to-Q delays of the two DFFs in a skew detection
circuit, the mismatch cannot be corrected and will show up as the timing skew of the
channel clock. We performed Monte Carlo simulations to measure the distribution of
the mismatch of the clock-to-Q delays of DFFs used in our design. The results are
shown in Fig. 10, where the x-axis represents the timing difference between ${\Phi}$$_{\mathrm{REF}}$
and ${\Phi}$$_{2}$, and the y-axis represents the probability of an UP signal (i.e.,
the probability that ${\Phi}$$_{2}$ is determined to have arrived earlier than ${\Phi}$$_{\mathrm{REF}}$).
We performed 100 iterations for each time difference. From Fig. 10, we estimate that the 1-sigma value of the residual skew from the clock-to-Q mismatch
is about 600 fs. Fig. 2 predicts that this would result in an SNR reduction of about 0.26 dB for a sinusoidal
input at the Nyquist frequency.
The mismatch between the threshold voltages (V$_{\mathrm{th}}$) of the sampling transistors
can contribute to effective timing jitter. The results of the Monte-Carlo simulations
indicate that the V$_{\mathrm{th}}$ mismatch is about 5 mV. This, when combined with
a 1/20-V/ps-slope of the sampling clock edge, produces jitter of about 100 fs. Therefore,
we expect that his should not degrade the jitter performance of 4-GS/s TI-ADCs.
Finally, the mismatches between routings for different channels are not calibrated
by this method and contribute to the residual skew. The mismatches include following:
i) those between the reference clock paths from the reference clock generator to D-FF
comparators, ii) those between the channel clock paths from D-FF comparators to the
sampling clock input of channel ADCs, iii) those between the signal paths to channel
ADC inputs. To estimate the skew from those mismatches, we performed post-layout simulations
while changing the length of the path. From the simulations, we found that even with
a very large path-length difference of 10 ${\mu}$m, the delay variation was less than
50 fs only. Therefore, we expect that the path-length mismatch should not degrade
the jitter performance of the envisioned TI-ADCs too much.
Fig. 3. Block diagram of the proposed skew calibration system.
Fig. 4. Proposed calibration logic flow.
Fig. 5. Proposed timing skew polarity detection circuit.
Fig. 6. Waveforms showing normal timing-skew polarity detection operation of CK2. (see to Fig. 5).
Fig. 7. Waveforms corresponding to ``forced decision'' operation of CK2 (see Fig. 5).
Fig. 8. Calibration logic output with digital code of delay line. D$_{2}$ is the digital code for the VDL for the 2$^{\mathrm{nd}}$ channel: (a) being calibrated; (b) after successful calibration.
Fig. 9. Movement of each channel clock and ${\Phi}$$_{\mathrm{REF}}$.
Fig. 10. Sensitivity to mismatch of two flip flops.
3. Circuit Implementation
Fig. 11 shows a block diagram of the clock generation circuit used in this work which produces
four channel clocks and the reference clock ${\Phi}$$_{\mathrm{REF}}$. The channel
clocks are produced by a current-mode logic CML frequency divider, of which the structure
is similar to that of [11]. The timing of the channel clocks are controlled by shunt-capacitor-inverter (SCI)
VDLs. In SCI VDLs, the delay is controlled by switching the bottom-plate connections
of the capacitors loading inverters. The resolution of the skew calibration is limited
by the step-size of the variable delay of VDLs. In II-1, it was observed that step-size
of 800 fs was needed to limit the SNR reduction to below 0.5 dB. In this work, step-sizes
of about 300 fs were used to secure margins. The delay of the reference clock is controlled
by a variable-path delay line which is suitable for a pico-second-range resolution.
When one of the VDL delays for the channel clocks reaches an end, the delay for ${\Phi}$$_{\mathrm{REF}}$
should be changed. Then, with the new ${\Phi}$$_{\mathrm{REF}}$ delay, the channel
clock VDL delays are adjusted again as already illustrated in Fig. 9. When the delays of a channel clock VDL and the reference clock VDL are changed simultaneously,
there is a risk that the delays interfere with each other generating oscillation at
the worst case. Especially in our circuit, the ‘end of the range’ signal is generated
by a sub channel circuit operating at f$_{\mathrm{s}}$/4 and kept HI for three reference
clock periods (=3T), while the reference clock VDL is adjusted every reference clock
period. Therefore, if the ‘end of the range’ signal is directly used for the reference
clock VDL adjustment, the VDL is adjusted in consecutive three steps producing large
transient perturbation which leads to oscillation.
Fig. 12 shows the circuit to prevent this and its timing diagram of operation. In Fig. 12, ER_U (or ER_L) represents the signal indicating that the counter for a channel clock
VDL reaches the upper (or lower) end. UP (or DN) is the signal input to the counter
for the coarse VDL to indicate that a 1-bit increase (or decrease) of the control
bits Q<2:0> for the coarse VDL is required. We can observe in the timing diagram in
Fig. 12, even though the ER_U signal has length of 3T, this circuit reduces the length of
UP (or DN) signal to one clock cycle. Therefore, for a single ‘end of range event’
the reference clock counter is activated only once.
Fig. 11. Block diagram of the clock generation system.
Fig. 12. Proposed structure to prevent undesired interactions between delays for channel clocks and the reference clock.