I. INTRODUCTION

Nanometer-order Complementary Metal-Oxide Semiconductor (CMOS) technology has driven the rapid development of mobile and wearable devices, such as smart phones and smart watches. Concurrent wearable devices have been used to monitor bio-signals for healthcare applications. Such wearable devices employ low-power analog-to-digital converters (ADCs) to interface the analog bio-signals from users with the digital signals required by micro-processing units (MPUs). These devices typically require low-power high-precision ADCs and multi-signal processing capabilities.

Recently, wearable devices have been actively studied to implement low-power and high-resolution hybrid ADCs ^[1-8]. Various architectures have been proposed in literature for low-power high-resolution hybrid ADCs, including flash-SAR, pipelined SAR, noise-shaping SAR, SAR-SS, and SAR-dual-slope (DS).

The power consumption and sampling rates of the SAR-SS and noise-shaping SAR architectures are lower than those of pipelined SAR and flash-SARs. The flash-SAR ^[1] and pipelined SAR ^[2] architectures offer high-speed conversion time and high resolution but suffer from high power consumption owing to the inherent natures of the flash and pipeline structures. However, noise-shaping SAR ^[3] and SAR-SS ^[4-6] architectures offer low-power and high-resolution characteristics with low-speed conversion time.

The noise-shaping SAR ADC in ^[3] showed ENOB of 14.2-bit and power consumption of 120 $\mu$W. The SS SAR hybrid ADC in ^[4] was shown to have a power consumption of 56 ${\mu}$W because of the ramp signal generator for the SS ADC to drive the capacitor digital-to-analog converter (C-DAC) inside the SAR ADC. In ^[5], the time-interleaved SAR-DS ADC was used to enhance signal processing speed and resolution, with a large power dissipation of 350 ${\mu}$W. In ^[6], the SS-SAR hybrid ADC determined MSB and LSB from the SS and SAR, respectively. This resulted in a poor linearity of +1.65/-1.45 LSBs. In ^[7], the SS ADC demonstrated better linearity than the SAR ADC. Consequently, the placement of the SAR structure for MSB and SS structure for LSB is expected to achieve low-power high-resolution hybrid ADC with good linearity.

This paper presents an architecture comprising a hybrid SAR and SS ADC with reconfigurability driven by a digital control circuit within the SS block. This allows the resolution and conversion speed of the proposed hybrid ADC to be reconfigured depending on the external resolution select signal. The proposed hybrid architecture shares analog blocks to minimize power consumption between the two segmented structures (SAR and SS). Section II describes the proposed hybrid architecture and algorithm. Section III presents the measurement results and comparisons of the measured performances with those from conventional architectures. Conclusions are drawn in Section IV.

II. PROPOSED ARCHITECTURE

The proposed reconfigurable SAR-SS ADC architecture includes a 14-bit C-DAC with a split capacitor (256/255 Cu), a latched comparator with a preamplifier, an 8-bit SAR logic, an SS block with bit select (BS) signal to reconfigure the resolution, a capture cell to store the y-bit signal from the y-bit binary counter, and an m-bit output register, as shown in Fig. 1.

In the conventional SAR ADC, the SAR logic generates all the input signals to the C-DAC. In the proposed design, the 8-bit SAR logic is connected to the 8-bit MSB of the C-DAC, and the y-bit binary counter is connected to the remaining 8-bit LSB of the C-DAC. Once the SAR logic is activated, the binary counter increments the output voltage of the C-DAC by 1 LSB per clock to generate a digital ramp starting from the residue voltage of the SAR ADC segments. The final SAR logic output bits are not reset to zero until the binary counter operation ends. The output data of the binary counter are captured when the digital ramp of the C-DAC crosses the common-mode voltage, and the output of the comparator is inverted with respect to its previous digital state. The 8-bit SAR logic and y-bit digital counter codes are produced simultaneously once the conversion process ends.

The block diagram presented in Fig. 2 represents the SS block of Fig. 1.

The SS block consists of the y-bit reconfigurable binary counter, Done generator, SS control circuit, and 10-clock counter with start-up circuit. After the 10-clock counter generates a pulse signal, the STATE signal from the SS control circuit enables the binary counter to activate the counter signal. The Done generator comprises a simple combination logic with a single D-flip flop that produces the Done signal at the end of the binary counter. The Boolean expression of the Done generator can be written as (1).

, where $B_{i}$ is the $i^{th}$ binary code of the binary counter.

The block diagram of the reconfigurable binary counter presented in Fig. 3 includes the binary counter and a decoder circuit. The decoder is capable of generating three RES signals ($RES_{0}$, $RES_{1}$, $RES_{2}$) to control six output signals ($B_{0}$, $B_{1}$, $B_{2}$, $B_{3}$, $B_{4}$, $B_{5}$). $RES\left[2\colon 0\right]$ can be described as

The remaining signals ($RES_{3}$, $RES_{4}$, $RES_{5}$) are unchanged at 1 since the upper three bits of the binary counter are not reconfigured. The decoder circuit is implemented as per the truth table given in Table 1.

The resolution of the reconfigurable binary counter can be determined by the state of the two-bit BS signal, as given in Table 2. The states 00, 01, 10, and 11 of the BS signals configure the binary counter resolution to 3-bit, 4-bit, 5-bit, or 6-bit.

As the binary counter activation ends, the bit-detection circuit produces the Done signal to reset the overall circuit, including the 10-clock counter with start-up circuit. The preamplifier is implemented to prevent kick-back noise from the latched comparator along with enhancement of the dynamic performance and linearity. The timing diagram of the proposed ADC is presented in Fig. 4.

As the Done signal becomes high, the reset generator becomes zero, C-DAC is fully discharged, and SAR logic commences operation. The BS signal determines the resolution (3–6 bit) of the binary counter in the SS ADC. As the 10-clock counter produces the SAR_Done signal, the 8-bit MSB of the C-DAC is determined and the STATE signal becomes high. Once the STATE signal goes high, the reconfigurable binary counter is changed according to the digital state of the BS signal. The binary counter in the SS ADC is connected to the LSB of the C-DAC, which increases the output voltage of the C-DAC during each clock to generate the digital ramp signal. If the binary counter becomes full, the STATE signal becomes low and Done signal becomes high to enable the 10-clock counter.

Fig. 1. Block diagram of the proposed m-bit reconfigurable SAR-SS ADC.

Fig. 2. Block diagram of the SS block.

Fig. 3. Block diagram of the reconfigurable binary counter.

Fig. 4. Timing diagram of the proposed ADC.

III. MEASUREMENT RESULTS

The chip photograph of the fabricated chip for the proposed ADC is shown in Fig. 5. The ADC is implemented in a standard CMOS 28-nm n-well 1-poly 8-metal process. The active chip area occupied $700\mu m\times 500\mu m$, excluding the bonding pads. The 14-bit C-DAC is placed atop the chip with a double guard for protection from the digital signals, and the latched comparator with preamplifier is placed adjacent to the C-DAC. The SS block, C-DAC control SAR logic circuit, y-bit binary counter, 8-bit SAR logic, and output register are placed at the bottom of the layout.

The photograph presented in Fig. 6 is the printed circuit board (PCB) with the proposed ADC. The PCB encloses two SMA connectors for the input signal (VIN) and clock signal (CLK), with analog power supply (AVDD, AVSS) and digital power supply (DVDD, DVSS). Two pins to apply the 2-bit BS signal and two test pins to measure the output of the comparator and SS block are placed at the center and on the edge of the right-hand side of the PCB, respectively. The 14-bit digital output pins are available at the bottom of the PCB.

The measured waveforms of the 2-bit BS (11, 10, 01, 00) and Done signals are presented in Fig. 7. The period time $t_{sample}$ of the Done signal associated with the 2-bit BS signal is designed to decrease approximately 1.5 times per bit.

The measured waveforms of the Done and comparator signals from the two test pins in Fig. 6 are presented in Fig. 8, as shown in Fig. 1. The rising edge of the Capture signal enables the capture cell to save the output data of the binary counter. These results verify the basic functionality and reconfigurability of the SS block and overall circuit.

The linearity (differential nonlinearity (DNL) and integral nonlinearity (INL)) of the reconfigurable ADC associated with the 14-bit mode (8-bit of SAR and 6-bit of SS) are measured as -0.96/+0.90 LSB and -0.73/+0.92 LSB, respectively. The analog and digital power consumption values of the ADC (14-bit mode) shown are measured to be 4.23 ${\mu}$W and 10.27 ${\mu}$W, respectively. As the proposed ADC is reconfigured by the external 2-bit BS signal to change a single bit, the digital power consumption of a single J/K flip flop associated with the bit is only increased by a negligible amount (of the order of a few nanowatt) compared to the total power consumption of 14.5 ${\mu}$W.

The measured Fast Fourier Transform (FFT) results are presented in Fig. 9 in order of the resolution (11–14 bit). The input and clock frequency are 1 kHz and 2 MHz, respectively. The 14-bit mode shows a signal to noise and distortion ratio (SNDR) of 76.5 dB and ENOB of 12.4 bit.

Fig. 10 illustrates the measured ENOB of 12.4 to 6.2-bit. The clock frequency varies from 100 kHz to 20 MHz with the input frequency fixed to 1 kHz. The measured ENOB stays close to 12.4-bit up to a clock frequency of 2 MHz and degrades thereafter. As the input frequency changes from 0.1 to 20 kHz with the clock frequency fixed to 26.7 kHz, the measured ENOB remains at almost 12.1-bit up to an input frequency of 2 kHz and decreases thereafter, as shown in Fig. 11.

A comparison of the static/dynamic performance parameters of the proposed hybrid ADC with those of the conventional ADC is made in Table 3. The proposed hybrid ADC shows a relatively low power consumption and comparable ENOBs with respect to the other hybrid devices ^[3-5]. The FoM of the proposed ADC is higher than those of the others owing to the low sampling rate. As observed, the conventional devices do not provide reconfigurability. On the other hand, the proposed ADC is capable of offering reconfigurable resolution (11–14 bit), so that it is applicable to several bio-signal processing cases.

Fig. 5. Chip photograph of the proposed reconfigurable ADC.

Fig. 6. Photograph of the proposed ADC on a PCB.

Fig. 7. Waveforms of the 2-bit BS (11, 10, 01, 00) and Done signals.

Fig. 8. Waveforms of Done and Capture signals (x=8, y=3).

Fig. 9. Measured FFT result for an input frequency of 1 kHz: (a) 11-bit, fs = 105.3 kS/s; (b) 12-bit, fs = 74.1 kS/s; (c) 13-bit, fs = 46.5 kS/s; (d)14-bit, fs = 26.7 kS/s.

Fig. 10. Plot of ENOB as a function of clock frequency ($f_{in}=1kHz$).

Fig. 11. Plot of ENOB as a function of the input frequency ($f_{sample}=26.7kS/s$).

IV. CONCLUSION

This paper presents a CMOS hybrid ADC with high resolution and reconfigurability for bio-signal processing. The proposed hybrid ADC consists of two segmented architectures, namely the SAR and SS architectures that are associated with the MSB and LSB, respectively. The SS block includes a reset generator, control circuitry, reconfigurable binary counter, and Done signal generator to enable reconfigurable resolution (11–14 bit) for the proposed ADC. The reconfigurable binary counter driven by an external two-bit signal can change the resolution of the proposed ADC, which is implemented on a standard CMOS 28-nm 1-poly 8-metal process. The active layout area occupied 700 ${\mathrm{\mu}}$m ${\times}$ 500 ${\mathrm{\mu}}$m, excluding the bonding pads. The measurement results demonstrated a power consumption of 14.5 ${\mu}$W (analog and digital power of 4.2~${\mathrm{\mu}}$W and 10.3 ${\mathrm{\mu}}$W, respectively), ENOB of 12.42 bit, DNL/INL of $\pm $0.96 LSB and $\pm $0.92 LSB, and FoM of 99.1 fJ/step.

The proposed hybrid ADC has the advantage of not only a reconfigurable architecture but also low power consumption owing to the segmented architecture compared to those of conventional hybrid ADCs. This ADC is expected to be employed in wearable devices for bio-signal processing and various IoT applications because of the reconfigurable resolution capability and low power dissipation.