I. INTRODUCTION

Following Moore's Law, the physical gate length (L$_{\mathrm{G, PHY}}$) of semiconductor devices continues to be scaled down to improve both output performance and dynamic power reduction. However, as device scaling continues, it inevitably leads to increased off-state current (I$_{\mathrm{OFF}}$) as well as standby power consumption, due to severed short-channel effects (SCEs) ^[1]. Accordingly, device architecture has changed from two-dimensional (2-D) planar field-effect transistors (FETs) to three-dimensional (3-D) FETs such as FinFETs and gate-all-around FETs (GAA FETs) ^[2-6].

The 3-D based device architecture increases gate oxide capacitance (C$_{\mathrm{OX}}$) by enlarging the surface area surrounding the channel. The increased C$_{\mathrm{OX}}$ improves gate controllability, hence the SCEs can be effectively suppressed. However, for cases where the L$_{\mathrm{G}}$ is extremely scaled down to a few nanometers level, a new device architecture, U-shaped channel FETs (UFETs), has been proposed ^[7].

The UFET has a buried gate electrode on a silicon substrate, which increases the effective gate length (L$_{\mathrm{G, EFF}}$) without sacrificing L$_{\mathrm{G, PHY}}$. It has been reported that several electrical characteristics of the UFET, such as the subthreshold swing (SS), are superior to that of GAA FETs ^[7]. Moreover, the fabrication process flow of the UFET is cost-effective compared with conventional 3-D architectures. Compared to GAA FETs, it is possible to reduce the number of processes, including the epitaxial growth step. In addition, the UFET has advantages in terms of device integration and cell height ^[8].

However, the UFET has several limitations, such as gate-induced-drain-leakage (GIDL) which stems from the drain (D)-to-gate (G) overlap region ^[9,10]. Also direct tunneling (DT) is unavoidable because the gate dielectric thickness is thin, and the distance between the source (S) and drain (D) is narrow as well ^[11]. Therefore, the UFET structure needs to be optimized to reduce the unwanted I$_{\mathrm{OFF}}$ caused by the GIDL and the direct tunneling (DT).

In this work, we conducted a study to optimize the structure and reduce the leakage current of the UFET. First, I$_{\mathrm{OFF}}$ was investigated with respect to L$_{\mathrm{G, PHY}}$ scaling. The impact of the gate spacer geometry and size to minimize I$_{\mathrm{OFF}}$ as well as I$_{\mathrm{G}}$ is discussed. Then, the doping concentration on the S/D regions was optimized with respect to the S/D module. Finally, substrate engineering is proposed, to reduce the leakage current from the Si-substrate by applying a vacuum dielectric.

II. EXPERIMENTAL DETAILS

Fig. 1 shows the UFET device structure used for the simulations. All of the simulations were performed using Synopsys Sentaurus. The Shockley-Read-Hall (SRH), bandgap narrowing, band-to-band tunneling (Hurkx), and Auger recombination were relected. Thin inversion layer, PhuMob, HighFieldSaturation, and Enormal were applied as the mobility models. The DirectTunneling and eBarrierTunneling models were selected to monitor the leakage current through the gate dielectric as well as the gate spacer.

Device geometries, materials, and doping concentrations were referred from previously reported papers ^[7,8]. It was assumed that L$_{\mathrm{G, PHY}}$ and equivalent oxide thickness (EOT) which is compsed of both HfO$_{2}$ and SiO$_{2}$ in the UFET, were 5 nm and 0.56 nm, respectively. Moreover, the gate spacer thickness (T$_{\mathrm{SPACER}}$) and depth (D$_{\mathrm{SPACER}}$) were 4 nm and 8 nm, respectively. Detailed device information is summarized in Table 1.

Fig. 1. Schematic of the UFET for TCAD simulations.

III. RESULTS AND DISCUSSIONS

Fig. 2 shows the I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristics and extracted gate leakage (I$_{\mathrm{G}}$) of the UFET with respect to gate module. Extracted device parameters such as V$_{\mathrm{TH}}$ and SS are summarized in the inserted table. The L$_{\mathrm{G, EFF}}$ indicates L$_{\mathrm{G, PHY}}$ + (2 ${\times}$ L$_{\mathrm{G, VER}}$). As the L$_{\mathrm{G, PHY}}$ scaled from 7 nm to 4 nm, V$_{\mathrm{TH}}$ decreased by 3.4% from 112.1 mV to 108.5 mV with 1.18 mV/nm sensitivity. On the other hand, SS increased by 113% from 92.8 mV/dec to 112.1 mV/dec due to severed SCEs. The S/D regions of the UFET are completely overlapped with the buried gate because of the device’s inherent structure. The degradation of reliability due to S/D overlapping is one of the concerns when developing the UFET ^[12].

In this context, Fig. 2(b) shows the I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristic with various T$_{\mathrm{SPACER}}$. When the T$_{\mathrm{SPACER}}$ is 0~nm. the extracted I$_{\mathrm{OFF}}$ at the off-state region (V$_{\mathrm{G}}$ = -~0.3~V) is 0.45 nA. However, as the T$_{\mathrm{SPACER}}$ was widened, the I$_{\mathrm{OFF}}$ decreased with 84 pA / nm sensitivity. The origin of the decreasing I$_{\mathrm{OFF}}$ is the reduced I$_{\mathrm{G}}$. In other words, the direct tunneling between the S/D overlapping and gate can be suppresed by widening the T$_{\mathrm{SPACER}}$, as shown in Fig. 2(c).

Fig. 2(d) shows the simulated current density profile with various T$_{\mathrm{SPACER}}$ when the off-state condition was V$_{\mathrm{D}}$ = 0.6 V and V$_{\mathrm{G}}$ = - 0.3 V. This confirmed that the current density in the drain region was significantly higher with the T$_{\mathrm{SPACER}}$ = 0 nm than with the 4 nm gate spacer. The severed leakage current resulting from DT can be effectively suppressed with an aid of a thicker gate spacer.

Fig. 3(a) shows the I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristics extracted with various gate spacer depths (D$_{\mathrm{SPACER}}$) in the range of 4 nm to 10 nm. The T$_{\mathrm{SPACER}}$ was fixed to 4 nm. With D$_{\mathrm{SPACER}}$ scaling, there were no remarkable changes in the values of SS and I$_{\mathrm{ON}}$. However, it was observed that the I$_{\mathrm{OFF}}$ increased as D$_{\mathrm{SPACER}}$ became shallow.

Fig. 3(b) shows the I$_{\mathrm{G}}$ for various D$_{\mathrm{SPACER}}$ thicknesses. When the D$_{\mathrm{SPACER}}$ is shallow (D$_{\mathrm{SPACER}}$ = 4 nm), the I$_{\mathrm{G}}$ increases at the overlap region at the gate-to-drain. The I$_{\mathrm{G}}$ resulting from the direct tunneling is proportional to the overlap area (tunneling width). However, by reducing the tunneling area by applying deeper D$_{\mathrm{SPACE}}$ (D$_{\mathrm{SPACER}}$ = 10 nm), the I$_{\mathrm{G}}$ can be suppressed.

Fig. 3(c) shows the simulated current profiles during the OFF state. The I$_{\mathrm{OFF}}$ caused by direct tunneling between the drain and gate gradually decreases when the D$_{\mathrm{SPACER}}$ reaches the drain junction depth of 10 nm. When applying a D$_{\mathrm{SPACER}}$ to a UFET, one should consider the junction depth to reduce the tunneling area.

In contrast to the previous results in this paper, which discuss the gate module, Fig. 4 shows the UFET characteristics in relation to the source/drain (S/D) doping concentrations (N$_{\mathrm{S/D}}$). Fig. 4(a) shows the simulated I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristics for various N$_{\mathrm{S/D}}$. As N$_{\mathrm{S/D}}$ decreases from 3 ˟ 10$^{20}$ cm$^{-3}$to 3 ˟ 10$^{18}$ cm$^{-3}$, the off-state current (I$_{\mathrm{OFF}}$) decreased from 8.85 pA to 0.33 pA with reduced SS. In other words, reducing the doping concentrations decreases depletion capacitance, which improves immunity to SCEs. However, the reduction in on-state current (I$_{\mathrm{ON}}$) and device output performance should be considered. In this context, Fig. 4(b) shows the I$_{\mathrm{ON}}$/I$_{\mathrm{OFF}}$ ratio for various N$_{\mathrm{S/D}}$. Considering the extracted I$_{\mathrm{ON}}$/I$_{\mathrm{OFF}}$ ratio, the optimum N$_{\mathrm{S/D}}$ was found to be 3 ${\times}$ 10$^{18}$ cm$^{-3}$ which maximized the suppression of SCEs compared to the rate of I$_{\mathrm{ON}}$ reduction.

The increased I$_{\mathrm{OFF}}$ resulting from the DT of the dielectrics as well as the PN junction were discussed in Fig. 2 to Fig. 4. However, another leakage current path flowing through the silicon substrate should be understood in UFETs.

Fig. 5(a) shows the electrical characteristics of a UFET fabricated on a silicon-on-nothing (SON) substrate ^[13]. The inserted vacuum layer was 20 nm wide, 5 nm high, and 2.5 nm away from the buried gate. 10 nm of D$_{\mathrm{SPACER}}$ and 4 nm of T$_{\mathrm{SPACER}}$ were applied to minimize the leakage current caused by the DT and junction leakage. The extracted I$_{\mathrm{OFF}}$ of the UFET fabricated on the SON substrate decreased by 65.5%, from 0.32 pA to 0.11 pA. Furthermore, SS decreased from 84.1 mV/dec to 70.4~mV/dec.

Fig. 5(b) shows the simulated current density profile under the off-state condition (V$_{\mathrm{D}}$ = 0.6 V and V$_{\mathrm{G}}$ = - 0.3 V). The inserted vacuum dielectric layer effectively isolates the leakage path between the source and drain, which enables the reduced I$_{\mathrm{OFF}}$.

Fig. 2. Simulated I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristics of the UFET based on the gate module design, with (a) L$_{\mathrm{G, PHY}}$; (b) T$_{\mathrm{SPACER}}$; (c) Extracted gate leakage with various T$_{\mathrm{SPACER}}$; (d) Simulated profiles of current density with different T$_{\mathrm{SPACER}}$.

Fig. 3. (a) Simulated I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristics of UFET with various gate spacer depths (D$_{\mathrm{SPACER}}$). Extracted (b) I$_{\mathrm{G}}$ and (c) current density.

Fig. 4. (a) Simulated I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristics of a UFET with various source/drain doping concentrations (N$_{\mathrm{S/D}}$); (b) Extracted I$_{\mathrm{ON}}$/I$_{\mathrm{OFF}}$ ratio.

Fig. 5. (a) Simulated I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristics of the UFET with a proposed silicon-on-nothing (SON) substrate; (b) Leakage current from the substrate (i) without and (ii) with the SON structure.

IV. CONCLUSIONS

This study conducted simulations of a U-shaped channel FET (UFET) with the goal of minimizing the off-state current (I$_{\mathrm{OFF}}$). It was observed that severed SCEs resulted from direct tunneling at the gate dielectric. Gate spacers were engineered with various thicknesses and depths. Subsequently, a thicker gate spacer is recommended. Moreover, the gate spacer depth should be similar in range to the junction depth to minimize the direct tunneling area. Considering the source/drain (S/D) doping concentrations, 3 $\times $ 10$^{18}$ cm$^{-3}$ is preferred for better I$_{\mathrm{ON}}$/I$_{\mathrm{OFF}}$ ratio. Excessive S/D doping concentrations degraded the SCEs without improving device performance. Finally, a novel device architecture containing a vacuum dielectric layer under the silicon substrate was proposed the suppress the leakage even further. It is possible that the I$_{\mathrm{OFF}}$ as well as SS can be improved with an aid of an inserted vacuum isolation.