I. INTRODUCTION

NAND flash memory is commercially available non-volatile memory and is used in various kinds of storage media ^[1-4]. Due to its low cost and high density, NAND flash memory based on floating-gate (FG) has successfully continued to reduce its feature size ^[5]. As the cell size of 2D NAND flash memory continued to shrink, it reached its miniaturization limit, which eventually led to the development of VNAND (vertical NAND) flash memory ^[3-5]. In VNAND, vertically stacked word-lines (WLs) run horizontally and channels are formed vertically. Due to the vertical channel structure, tube-type poly-Si channels are used, and the p-well that supplies holes for an erase operation to lower the V$_{\mathrm{th}}$ of the cell cannot be implemented ^[6-8]. Therefore, erase operation using gate-induced drain leakage (GIDL) has been developed ^[6-9].

Fig. 1 shows the pulse diagram for erasing NAND flash memory cells using GIDL. A high erase voltage (V$_{\mathrm{Erase}}$) is applied to the bit-line (BL) and the source-line (SL) at both ends of the VNAND cell string ^[9,10]. A voltage lower than V$_{\mathrm{Erase}}$ is applied to the gate of devices such as the drain select line (DSL) and source select line (SSL) that can selectively connect a cell string to BL/SL. The potential difference between BL and DSL (or the potential difference between SL and SSL) becomes the V$_{\mathrm{GIDL}}$ (V$_{\mathrm{BL}}$\textendash{}V$_{\mathrm{DSL}}$ or V$_{\mathrm{SL}}$\textendash{}V$_{\mathrm{SSL}}$) for the hole generation. The holes generated by GIDL at both ends of the cell string spread to the middle of the channel, and are stored in the charge storage layer (Si$_{3}$N$_{4}$ layer) through tunneling by the potential difference between the WL and channel of the cell for erase, thereby reducing the V$_{\mathrm{th}}$ of the cell. Therefore, if hole generation by GIDL is insufficient, the erase operation is not performed properly ^[1]. A one-bit erase operation that erases only one cell in a VNAND flash memory structure by creatively using the above characteristics has been proposed in a previous study ^[10]. In ^[10], it is necessary to study how V$_{\mathrm{GIDL}}$ affects V$_{\mathrm{th}}$ change based on the physics in terms of cell devices and strings.

In this paper, the analysis of the erase characteristics of VNAND cells is done by TCAD simulation and its operation mechanism is described. In the case of simulation, the V$_{\mathrm{th}}$ change after the erase operation is corrected by adjusting the physical parameters to match the measurement result. Using the calibrated simulation results, the erase characteristics of VNAND and its determining factors are analyzed.

Fig. 1. Pulse diagram for erasing NAND flash memory cells. V$_{\mathrm{Erase}}$ is applied to BL and SL. A voltage lower than V$_{\mathrm{Erase}}$ is applied to DSL and SSL. t$_{1}$ and t$_{2}$ are the time when V$_{\mathrm{BL}}$ and V$_{\mathrm{SL}}$ become V$_{\mathrm{Erase}}$ and the time when V$_{\mathrm{BL}}$ and V$_{\mathrm{SL}}$ start to decrease from V$_{\mathrm{Erase}}$, respectively.

II. ARCHITECTURE

Fig. 2 shows (a) the cross-sectional view of VNAND, (b) implemented model with half of the cross-section of VNAND by Sentaurus$^{\mathrm{TM}}$-based TCAD simulation ^[11-15], and (c) circuit schematic of the model, respectively. BL is connected to the upper part of the cell string and SL is connected to the lower part. DSL and SSL are arranged as select line switches adjacent to BL and SL, respectively, and WLs are stacked vertically between DSL and SSL. In Fig. 2(a), the vertical cell string consists of filler oxide, polysilicon, tunnel oxide, trap Si$_{3}$N$_{\mathrm{4,}}$ and blocking oxide [3, 6-8]. The regions where BL and SL are connected are heavily doped with n-type impurity [6, 7, 16]. The model consists of 8 WLs, and the cell of the 4$^{\mathrm{th}}$ WL from the top is selected. The cylindrical coordinate system is applied to the TCAD simulation. During the erase operation, 0 V is applied to the selected WL, and 6 V is applied to unselected WLs for erase inhibition.

Fig. 2. (a) Cross-sectional view of a VNAND string; (b) implemented model with half of the cross-section of VNAND by TCAD simulation; (c) circuit diagram of the model. The model consists of 8 WLs. x represents the radius from the center of the cylinder, and y represents the depth from BL contact to SL contact.

III. RESULT AND DISCUSSION

Fig. 3 compares the measured and simulated ${\Delta}$V$_{\mathrm{th}}$’s (= V$_{\mathrm{th}}$ before erase\textendash{}V$_{\mathrm{th}}$ after erase) as a function of V$_{\mathrm{GIDL}}$. In the VNAND memory mass-produced by the company, ${\Delta}$V$_{\mathrm{th}}$ dependent on V$_{\mathrm{GIDL}}$ is measured. In the measurement and simulation, the cell before the erase operation is in a neutral state, cell V$_{\mathrm{th}}$ is 0 V ^[17], and V$_{\mathrm{Erase}}$ is 18 V. The ${\Delta}$V$_{\mathrm{th}}$ obtained from the TCAD simulation is similar to the measured value under various V$_{\mathrm{GIDL}}$’s and thus well describes the erase behavior of the experimental device. As V$_{\mathrm{GIDL}}$ increases above 2 V, ${\Delta}$V$_{\mathrm{th}}$ begins to increase significantly. When V$_{\mathrm{GIDL}}$ becomes 3 V or higher, ${\Delta}$V$_{\mathrm{th}}$ of NAND memory cells becomes 0.6 V or higher. When V$_{\mathrm{GIDL}}$ decreases below 2 V, ${\Delta}$V$_{\mathrm{th}}$ of the cell is reduced below 0.1 V. ${\Delta}$V$_{\mathrm{th}}$ is minimal when V$_{\mathrm{GIDL}}$ is 1 V. When V$_{\mathrm{GIDL}}$ is 0 V, ${\Delta}$V$_{\mathrm{th}}$ is slightly greater than its minimum value when V$_{\mathrm{GIDL}}$ is 1 V. An erase operation with GIDL (V$_{\mathrm{GIDL}}$ of 6 V) has a 10 times larger ${\Delta}$V$_{\mathrm{th}}$ than an erase operation without GIDL (V$_{\mathrm{GIDL}}$ of 0 V).

To further investigate the effect of V$_{\mathrm{GIDL}}$ on the erase characteristics when the BL/SL bias becomes V$_{\mathrm{Erase}}$ during erase pulse (t$_{1}$ in Fig. 1), the channel potential at the interface between the channel and the tunnel oxide (Fig. 4(a)) and the GIDL generation induced by band-to-band tunneling (Fig. 4(b)) are analyzed. Since the same V$_{\mathrm{Erase}}$ is applied to the BL and SL, the potentials at both ends of the channel become the same. The regions between the two vertical dashed lines on the left and right of Fig. 4 indicate the gate positions of DSL and SSL, respectively, and the channel potential changes greatly in these regions. The channel potential of the WLs is almost identical regardless of their locations. As V$_{\mathrm{GIDL}}$ increases by decreasing V$_{\mathrm{DSL}}$ (or V$_{\mathrm{SSL}}$), the WL channel potential decreases. Since GIDL is generated by the potential difference between BL (or SL) and DSL (or SSL), GIDL is generated in the DSL/SSL region and rarely in the WL region. As V$_{\mathrm{GIDL}}$ increases, the potential difference between BL and DSL (or the potential difference between SL and SSL) increases, and GIDL generation also increases.

Fig. 5(a) and (b) show ${\Delta}$V$_{\mathrm{th}}$ vs. channel potential and ${\Delta}$V$_{\mathrm{th}}$ vs. GIDL generation, respectively. The channel potential is obtained from the channel of the selected WL cell, and the value that generates the largest GIDL among V$_{\mathrm{GIDL}}$ conditions is used. Fig. 5(a) shows that larger channel potential reduces the ${\Delta}$V$_{\mathrm{th}}$ within a channel potential of about 11 V. Fig. 5(b) shows ${\Delta}$V$_{\mathrm{th}}$ increases as GIDL generation increases. When V$_{\mathrm{GIDL}}$ becomes larger than or equal to 3 V, the GIDL generation rate is larger than 10$^{25}$ cm$^{-3}$ s$^{-1}$ and ${\Delta}$V$_{\mathrm{th}}$ also increases as the GIDL generation increases. When V$_{\mathrm{GIDL}}$ becomes less than or equal to 2 V, GIDL generation is less than 10$^{24}$ cm$^{-3}$ s$^{-1}$ and ${\Delta}$V$_{\mathrm{th}}$ is small. Abovementioned results show that the GIDL generation is more critical than the channel potential for the erase operation using GIDL in VNAND flash memory. Therefore, the one-bit erase operation, which lowers the V$_{\mathrm{th}}$ of only the selected cell\st{s}, increases the V$_{\mathrm{DSL}}$ of the unselected DSL even if a high bias of V$_{\mathrm{Erase}}$ is applied to the selected BL, thereby reducing the V$_{\mathrm{GIDL}}$.

Fig. 6(a) shows the channel potential at t$_{2}$ when the erase operation ends and V$_{\mathrm{BL}}$=V$_{\mathrm{SL}}$ begins to decrease. Compared to the result of Fig. 4(a), the channel potential at t$_{2}$ became larger than that at t$_{1}$. The holes generated by GIDL have a positive charge and move toward the channel ^[6]. As the number of holes in the channel increases, the channel potential increases even though V$_{\mathrm{BL}}$ and V$_{\mathrm{SL}}$ are constant. Therefore, the channel potential is higher at t$_{2}$ than at t$_{1}$. The trend of the channel potential depending on V$_{\mathrm{GIDL}}$ in the inset of Fig. 6(a) is similar to that of ${\Delta}$V$_{\mathrm{th}}$ after erase operation depending on V$_{\mathrm{GIDL}}$ in Fig. 3. Fig. 6(b) shows the channel potential difference between t$_{1}$ and t$_{2}$ depending on GIDL generation at t$_{1}$. The nonlinear relationship between V$_{\mathrm{GIDL}}$ and ${\Delta}$V$_{\mathrm{th}}$ can be explained by the channel potential at the beginning of the erase pulse (t$_{1}$ in Fig. 1) and the channel potential increase due to GIDL generation. When V$_{\mathrm{GIDL}}$ is 1 V or less, the channel potential increase by GIDL generation is small, so the channel potential at t$_{1}$ affects the ${\Delta}$V$_{\mathrm{th}}$. On the other hand, when V$_{\mathrm{GIDL}}$ is 3 V or more, the channel potential at t$_{1}$ is relatively low, but the increase in channel potential by GIDL generation is large, so the change in ${\Delta}$V$_{\mathrm{th}}$ is large.

Fig. 3. Comparison of measured and simulated ${\Delta}$V$_{\mathrm{th}}$ after the erase operation. In both measurement and simulation, V$_{\mathrm{Erase}}$ is 18 V and cell V$_{\mathrm{th}}$ before erase operation is 0 V.}

Fig. 4. Simulated: (a) channel potential; (b) GIDL generation when BL/SL bias becomes V$_{\mathrm{Erase}}$ (t$_{1}$ in Fig. 1). The regions between the two vertical dashed lines on the left and right indicate the gate locations for DSL and SSL, respectively. Insets in (a) and (b) represent channel potential vs. V$_{\mathrm{GIDL}}$ and GIDL generation vs. V$_{\mathrm{GIDL}}$, respectively.

Fig. 5. ${\Delta}$V$_{\mathrm{th}}$ vs.: (a) channel potential; (b) GIDL generation at t$_{1}$.

Fig. 6. (a) Simulated channel potential at t$_{2}$. Inset represents channel potential vs. V$_{\mathrm{GIDL}}$ at t$_{2}$; (b) channel potential difference between t$_{1}$ and t$_{2}$ vs. GIDL generation at t$_{1}$.

IV. CONCLUSIONS

In order to understand the erase characteristics of VNAND cells depending on V$_{\mathrm{GIDL}}$, an analysis of VNAND cell erase considering channel potential and GIDL generation has been reported. The hole generation by GIDL at the beginning of erase pulse has a large influence on the ${\Delta}$V$_{\mathrm{th}}$ of the VNAND cells. Through these results, the selective 1-bit erase operation, which reduces only the V$_{\mathrm{th}}$ of the selected cell in VNAND by adjusting the amount of GIDL generation, was verified.