1. Gate Step Voltage Stress

Step voltage stress was conducted within a temperature range of 25 ℃ to 125 ℃ to ascertain the breakdown voltage. The gate stress voltage was incrementally raised in the steps of 0.5 V with V$_{\mathrm{DS}}$=0 V until gate stress current reached current compliance (20 mA), and each gate stress voltage was applied for a duration of 120 seconds as shown in Fig. 2(a). The short-term step voltage stress test has been widely employed to investigate the degradation of GaN power devices. He et al. ^[20] evaluated the robustness of p-GaN gate against forward gate bias and found the breakdown voltage through the sudden increase of gate current by a step-stress measurement. Rossetto et al. ^[21] also observed the generation of defect-related conduction processes and the catastrophic failure through a sudden increase of the gate forward current at the breakdown voltage by step stress experiments. The transfer characteristics was measured after each stress test and the gate stress current (I$_{\mathrm{g.stress}}$) was monitored during the stress test to confirm the device failure as shown Fig. 2(b). We defined a sudden rise in the gate stress current as device failure. Significant increases in the gate stress current were observed with 10, 10.5, 11, and 11.5 V at temperatures of 25, 75, 100, and 125 ℃, respectively. The devices exhibited a higher breakdown voltage at higher temperature, suggesting the degradation mechanism induced by forward gate bias in p-GaN gate HEMTs has a dependence on the temperature. Furthermore, the device failure was verified by examining the transfer characteristics measured after the stress test. After the 11.5 V-stress test at 125 ℃, both the drain off-current and gate leakage current exhibited a substantial increase as shown in Fig. 3(a) and (b) while both the drain off-current and gate leakage current maintained low levels similar to those seen in the initial device up to 11 V. This ensures abrupt nature of GaN HEMTs degradation. To analyze this degradation mechanism in detail, constant voltage stress measurements was performed at varying stress voltages and temperatures.

Fig. 2. (a) Schematic of gate step voltage stress; (b) Gate stress current during step voltage stress at different temperatures.

Fig. 3. (a) ID-VGS; (b) IG-VGS characteristics before and after step voltage stress at 125 ℃.

2. Time-dependent Degradation

To investigate the time-dependent degradation mechanism induced by forward gate bias, constant voltage stress was conducted by applying V$_{\mathrm{g.stress}}$ of 9.2, 9.4, and 9.6 V with V$_{\mathrm{DS}}$=0 V at room temperature. The determination of the gate stress voltage was based on the breakdown voltage acquired from the step voltage stress. These determined voltages were applied until a substantial increase in the gate stress current was observed. The gate stress current was monitored during the constant voltage stress to confirm the catastrophic rise of the gate stress current, which acts as an indicator of device breakdown. Time-to-failure (TTF), t$_{\mathrm{BD}}$, is defined as the time when the device experiences failure, demonstrated by an increase in both the drain-off current and gate leakage current (not shown in this paper). T$_{\mathrm{BD}}$ of Schottky-type p-GaN gate HEMTs follows a Weibull distribution under constant voltage stress, as reported in the studies involving Si MOSFETs ^[22] and typical GaN HEMTs ^[23,24]. Fig. 4(b) presents a Weibull plot of t$_{\mathrm{BD}}$ for various stress voltages. The shape factor (${\beta}$) was extracted within the range of 1.08 to 1.89, and the mean-time-to-failure (MTTF) was found to be 11,220, 1,804 and 352 seconds for stress voltages of 9.2, 9.4 and 9.6 V, respectively. By analyzing MTTF at various stress voltages, we derived an estimate for the maximum applicable gate voltage of 8 V at room temperature, employing the exponential law (E-model) as shown in Fig. 4(c). The exponential law has a robust dependence on the electric field and temperature, where t$_{\mathrm{BD}}$ is expected to exhibit an exponential relationship with the gate stress voltage ^[25,26]. Under this specific condition, the device is anticipated to have a functional lifetime of 10 years with a 63% failure rate.

Fig. 4. (a) Gate stress current during constant voltage stress; (b) Weibull plot of tBD for various stress voltages; (c) Estimation of the maximum applicable gate voltage for the lifetime of 10 years with a 63 % failure rate.

3. Temperature-dependent Degradation

Constant gate voltage stress was conducted with V$_{\mathrm{g.stress}}$ of 10 V at 75, 100, and 125 ℃ to examine the temperature dependence of time-dependent degradation. The initial value of the gate stress current does not exhibit temperature dependence at a high gate voltage of 10 V as shown in Fig. 5(a). This observation indicates that the dominant gate conduction mechanism is field-dependent such as Fowler-Nordheim tunneling in the high gate bias regime. When a forward gate bias is applied, a number of holes can migrate from the gate electrode into the p-GaN layer via Fowler-Nordheim tunneling and affect to the time-dependent degradation ^[27,28]. The Weibull plot of t$_{\mathrm{BD}}$ is illustrated for various temperatures as shown in Fig. 5(b). The extracted MTTF values are 116, 4,728 and 26,752 seconds for temperatures of 75, 100, and 125 ℃, respectively. Longer lifetimes are observed at elevated temperatures, which demonstrates that time-dependent degradation is temperature-dependent and alleviated by high temperatures. The shape factor is determined to be 2.77, 2.69, and 1.49 for 75, 100, and 125 ℃, respectively. The shape factor diminished at higher temperatures compared to room temperature. Degraeve et al. ^[29] and Meneghesso et al. ^[30] discussed that there are two modes of breakdown, electrical stress induced defects generation-related intrinsic breakdown and the initial defect-related extrinsic breakdown. A small shape factor suggests that the device failure is likely due to extrinsic breakdown induced by process defects, while a large shape factor suggests that the device failure is more likely due to intrinsic breakdown induced by electrical stress. The lower shape factor at 125 ℃ implies that the time-dependent degradation mechanisms are associated with the existence of initial defects rather than the generation of new defect sites at elevated temperatures. This result demonstrates that the forward gate bias induced degradation mechanisms is alleviated at high temperature compared to room temperature. The Arrhenius plot obtained from MTTF at various temperatures is shown in Fig. 5(c). A negative activation energy of -1.2 eV is estimated from the Arrhenius plot, which demonstrates that p-GaN gate HEMTs have a positive temperature dependence on time-dependent degradation induced by forward gate bias. This observation is a unique result not seen in Si MOSFET and conventional AlGaN/GaN HEMTs. This outcome can be attributed to the injected holes at the Schottky junction.

When a forward gate bias is applied, the steeper band bending within the p-GaN layer can facilitate the tunneling of holes from the gate electrode toward the p-GaN layer as shown in Fig. 6. As these holes reach the p-GaN/AlGaN interface, holes tend to accumulate and be trapped at the hole trap site. Rossetto et al. ^[31] investigated the field- and current-driven degradation of p-GaN gate HEMTs depending on Mg-doping level. This study reported the presence of hole traps both at the p-GaN/AlGaN interface and within the AlGaN barrier. The positive charges induced by these accumulation and trapping of holes in the p-GaN and AlGaN layers lower the energy barrier of the AlGaN conduction band edge. Consequently, certain electrons in the 2DEG channel are able to spill over the AlGaN barrier and transfer toward the depleted region of the p-GaN layer as shown in Fig. 6(a). Some of the injected electrons can recombine with holes in the non-depleted region. Both holes and electrons that reach the depleted p-GaN region without recombining are accelerated by a high electric field of the reverse-biased Schottky junction. These accelerated hot carriers (holes and electrons) contribute to the degradation of the p-GaN gate stack by generating the new defect sites through impact ionization ^[11]. The gate stress current shows a severe increase due to the leakage conduction path created by the generated defects in the depleted p-GaN region as shown in Fig. 4(a). However, the holes trapped at the p-GaN and AlGaN layers acquire significant energy by high temperature and can be released from the trap states (de-trapping process) at elevated temperatures as shown in Fig. 6(b) ^[32]. The energy barrier of the AlGaN conduction band edge is higher due to the removal of positive charge at elevated temperature compared to room temperature. As a result, the emission of electrons from the 2DEG channel toward the p-GaN layer is hindered. Furthermore, the thermal scattering of carriers is notably enhanced in the depleted p-GaN region, resulting in carriers being less capable of accelerating sufficiently. Consequently, the generation of hot carriers and new defects is significantly diminished due to an enhancement of thermal scattering driven by elevated temperatures. As illustrated above, the alleviation in time-dependent degradation at high temperatures was demonstrated by the longer lifetime, small shape parameter and negative activation energy.

Fig. 5. (a) Gate stress current during constant voltage stress; (b) Weibull plot of tBD; (c) Arrhenius plot for various temperatures.

Fig. 6. Schematic band diagrams of Schottky p-GaN gate AlGaN/GaN HEMT at (a) room temperature; (b) high temperature.