I. INTRODUCTION

Si-based power electronic devices, such as insulated gate bipolar transistors (IGBTs) and superjunction metal- oxide-semiconductor field-effect transistors (MOSFETs) ^[1], have been widely used as high-power and frequency electronic devices. However, these devices have certain physical limitations, and their power density is reaching its saturation limit ^[2]. Therefore, studies have suggested the use of gallium nitride (GaN) and related wide-bandgap semiconducting alloys as candidate materials for the next-generation high-power and frequency electronic devices ^[3,4]. Compared with Si, the higher breakdown field and drift velocity of GaN-based devices can produce lower losses at high voltages and temperatures ^[5,6]. Power GaN devices are typically grown on an Si or sapphire substrates to minimize cost and maximize yield ^[7]. However, the commercial use of high-quality bulk GaN substrates has recently become widespread, enabling the development of vertical GaN-on-GaN devices. The GaN-on-GaN substrate features zero lattice mismatch between the epitaxial layer and substrate, thus allowing to obtain a GaN drift layer with a larger thickness and lower dislocation density (Table 1) ^[19].

The lattice mismatch between the coefficients of thermal expansion of the epilayers and substrate results in wafer bowing, which in turn could hinder the fabrication process. Thus, a lower thermal resistance can be achieved in GaN-on-GaN substrates ^[20], where the defect density owing to a lattice constant mismatch is very low, making them suitable for high-voltage and high-power devices.

Lateral GaN power devices (e.g., GaN high electron- mobility transistors and lateral GaN diodes based on 2D electron gas) have been extensively studied, with the development of commercial transistors with operating voltages up to 650 V ^[8]. However, the power handling of the lateral GaN power devices is typically limited to a few kW. Furthermore, it suffers from problems associated with the lateral current flow near the buffer layers and overlying dielectric layers. These well-known issues include avalanche breakdown ^[21]. The applicability of the vertical GaN power devices is being expanded to voltages beyond 650 V and current beyond 100 A. In addition, the longer the distance between the gate and drain regions in the power transistor (D$_{\mathrm{gd}}$), the higher the breakdown voltage (BV) that can be obtained. Thus, compared with the lateral structure, a vertical power device has several advantages. High-electron-mobility transistors (HEMTs) are typical representative of GaN-based devices. The lateral GaN HEMTs based on a AlGaN/GaN heterostructure are typically normally-on devices ^[9]. To obtain a normally-off operation, either a p-type GaN layer or a recessed gate structure is required on the undoped AlGaN layer ^[10-12]. However, in junctionless field-effect transistors (JLFETs), the normally -off operation can be implemented without the p-type GaN layer ^[13,14]. Moreover, the JLFETs are less sensitive to surface trapping than other transistors.

Herein, simulations were conducted to compare the performances of the vertical cylinder- and fin-type GaN JLFETs using a GaN-on-GaN substrate. Moreover, the figure of merits, such as the static resistance (R$_{\mathrm{on}}$) and BV, were investigated. Herein, we provide insight into not only the electrical properties of the GaN-on-GaN-based vertical GaN JLFETs but also the design guidelines of power transistors.

II. EXPERIMENTAL PROCEDURE

Fig. 1(a) and (b) shows the 3D structures, and Fig. 1(c) and (d) shows the cross-sectional views of the vertical cylinder- and fin-type GaN JLFETs based on a GaN-on-GaN substrate. Table 2 summarizes the parameters used in this study. The structures of the vertical cylinder- and fin-type GaN JLFETs comprise a 10 ${\mathrm{\mu}}$m-thick n -GaN substrate (T$_{\mathrm{sub}}$), 200 nm-thick n$^{+}$-GaN layer (T$_{\mathrm{N}}$), 12 ${\mathrm{\mu}}$m-thick u -GaN drift layer (T$_{\mathrm{drift}}$), and 700 nm gate length (L$_{\mathrm{g}}$). Moreover, the oxide thickness (T$_{\mathrm{ox}}$) is 15 nm, with a 300 nm n$^{+}$-GaN thickness (T$_{\mathrm{source}}$) and 100 nm-diameter channel (D$_{\mathrm{ch}}$). The substrate length (L$_{\mathrm{sub}}$) is 500 nm. The work functions of the gate electrode metal of the vertical cylinder- and fin-type GaN JLFETs were 5.15 and 3.1 eV, respectively. The n -GaN and n$^{+}$-GaN (T$_{\mathrm{N}}$) of the n-type doping concentration were 5 ${\times}$ 10$^{17}$ and 2 ${\times}$ 10$^{18}$ cm$^{\mathrm{\hbox{-}3}}$, respectively. Moreover, the u -GaN and n$^{+}$-GaN (T$_{\mathrm{source}}$) of the n-type doping concentration were 1 ${\times}$ 10$^{16}$ and 3 ${\times}$ 10$^{18}$ cm$^{\mathrm{\hbox{-}3}}$, respectively. In addition, the fin width (W$_{\mathrm{fin}}$) of the vertical fin-type GaN JLFET was 100 nm, and SiO$_{2}$ was used as the insulating oxide. As shown in Fig. 1, A-A’ represents the cutline in the lateral direction based on the channel center of each device and is used to determine the distribution of the electron concentration at its off-sate (V$_{\mathrm{GS}}$ = 0 V). Furthermore, B-B’ represents the cutline in the vertical direction between the channel region and oxide interface of each device; it determines the distribution of the electric field at V$_{\mathrm{DS}}$ = 1,500 V. Accordingly, we analyzed the performances of the vertical cylinder- and fin-type GaN JLFET-based GaN-on-GaN substrates. In addition, we conducted three-dimensional technical computer-aided design (3D TCAD) simulations of Fermi-Dirac, a Shockley-Read-Hall recombination. To increase the accuracy of the simulation, we used low-field-mobility, high-field-mobility, and impact ionization models ^[22,23].

Fig. 1. (a) Vertical cylinder-type GaN JLFET 3D structure; (b) Vertical fin-type GaN JLFET 3D structure Cross-sectional views of the (c) vertical cylinder-type GaN JLFET; (d) vertical fin-type GaN JLFET.

III. RESULTS AND DISCUSSION

Fig. 2(a) shows the linear and logarithmic transfer curves (I$_{\mathrm{D}}$-V$_{\mathrm{GS}}$), and Fig. 2(b) shows the output curves (I$_{\mathrm{D}}$-V$_{\mathrm{DS}}$) of the two GaN JLFETs based on the GaN-on-GaN substrate at the drain voltage of V$_{\mathrm{DS}}$ = 5 V. The on-current (I$_{\mathrm{on}}$) is defined as a current value corresponding to V$_{\mathrm{G}}$ = 7 V. The normalization method of the drain current (I$_{\mathrm{D}}$) and static resistance (R$_{\mathrm{on}}$), comprising DC resistance and BV was based on the substrate area.

The on-current (I$_{\mathrm{on}}$), which is related to the resistances of the channel (R$_{\mathrm{ch}}$), drift layer (R$_{\mathrm{drift}}$), n$^{+}$-GaN layer (R$_{\mathrm{n+}}$), and substrate (R$_{\mathrm{sub}}$), of the vertical cylinder- and fin-type were 6.45 and 5.63 kA/cm$^{2}$, respectively. The total resistance (R$_{\mathrm{total}}$) is the sum of R$_{\mathrm{drift}}$, R$_{\mathrm{n}}$, and R$_{\mathrm{sub}}$. Fig. 3 shows the schematic of R$_{\mathrm{ch}}$ and R$_{\mathrm{total}}$. The change in the I$_{\mathrm{on}}$ and the R$_{\mathrm{on}}$can be explained in terms of the resistance structure of the fin-type device. The resistance values were extracted using simulations to achieve R$_{\mathrm{ch}}$ = 0.155 m${\Omega}$·cm$^{2}$, and R$_{\mathrm{drift}}$ = 0.827 m${\Omega}$·cm$^{2}$, R$_{\mathrm{n+}}$ = 0.0005 m${\Omega}$·cm$^{2}$, and R$_{\mathrm{sub}}$= 0.024 m${\Omega}$·cm$^{2}$; therefore, the total resistance value of the substrate can be calculated as 0.852 m${\Omega}$·cm$^{2}$ ^[9,18]. As shown, the R$_{\mathrm{ch}}$ value is smaller than the R$_{\mathrm{total}}$ value because the carrier concentration of the channel region is relatively higher than that of the R$_{\mathrm{total}}$ region. Therefore, the determination of the on-current (I$_{\mathrm{on}}$) depends on the substrate area. This is because the resistance and area have a trade-off relationship, which affects the on-current corresponding to Ohm’s law. Thus, the total current is dependent on the substrate area. Fig. 2(b) shows the I$_{\mathrm{D}}$-V$_{\mathrm{DS}}$ characteristics of the R$_{\mathrm{on}}$calculated in the linear region with V$_{\mathrm{DS}}$ = 0.1 V and V$_{\mathrm{GS}}$ = 6 V. Thus, for the vertical cylinder-type device, R$_{\mathrm{on}}$ = 0.11 ${\mathrm{\mu}}$${\Omega}$·cm$^{2}$, which is lower than R$_{\mathrm{on}}$ = 0.62 ${\mathrm{\mu}}$${\Omega}$·cm$^{2}$ of the vertical fin-type device. This is because the vertical cylinder-type device has the largest slope value at V$_{\mathrm{GS}}$ = 6 V. Furthermore, the threshold voltage (V$_{\mathrm{t}}$) was calculated using the g$_{\mathrm{m,max}}$ method, and the V$_{\mathrm{t}}$ of the vertical cylinder- and fin-type devices were calculated as 1.26 and 1.35 V, with the corresponding subthreshold swings (SSs) of 101 and 346 mV/dec, respectively. The I$_{\mathrm{on}}$/I$_{\mathrm{off}}$ ratio of the two devices was 2.57 ${\times}$ 10$^{13}$ and 5.79 ${\times}$ 10$^{4}$, respectively, which could be attributed to the structure features ^[16].

Herein, simulations were performed on the vertical GaN JLFETs. Unlike MOSFETs, the operating principle of a JLFET adds a bias to the gate to reduce the depletion effect, thus forming a channel to allow current flow. The JLFETs are normally designed to operate under a flat-band condition in the on state ^[17]. A significant number of carriers flow in the channel bulk and are less affected by surface scattering and interface traps. When the gate voltage (V$_{\mathrm{GS}}$) is 0 V, full depletion must be achieved in the channel region to completely inhibit the majority carrier current flow from drain to source ^[16]. Furthermore, the depletion of majority carriers results in very low conductivity during off-state operation. Therefore, the leakage current is determined by the gate-induced depletion of the channel region. Thus, in structures such as gate-all around (GAA) structures full depletion could be easily achieved if gate controllability is enhanced. Unlike the vertical fin-type GaN JLFET, the vertical cylinder-type has a different gate area that is in contact with the channel. In addition, it possesses a GAA structure in which all areas of the channel are surrounded by gates. Therefore, the channel area is relatively larger than that of the vertical fin-type GaN JLFET. These findings suggest that the vertical cylinder-type GaN JLFET has a turn-off higher than that of the vertical fin-type GaN JLFET. Fig. 4(a) and (c) demonstrates the channel regions in the off-state (V$_{\mathrm{GS}}$ = 0 V), as represented by the dotted line in Fig. 3. Fig. 4(b) and (d) represents the energy-band diagrams from A to A’. The electron quasi-fermi level (F$_{\mathrm{N}}$) was calculated to determine the concentration of electrons, which are a majority carrier, to determine which of the regions in Fig. 4(b) and (d) has a higher turn-off. Compared with the vertical fin-type, the vertical cylinder-type GaN JLFET shows a smaller energy potential value between the conduction band (E$_{\mathrm{C}}$) and F$_{\mathrm{N}}$. As both JLFETs are in the off-state (V$_{\mathrm{GS}}$ = 0 V), the electron concentration value itself is small; however, the potential energy value of the electrons in the vertical cylinder-type GaN JLFET is relatively large. In addition, I$_{\mathrm{off}}$ = 2.51 ${\times}$ 10$^{\mathrm{\hbox{-}10}}$$_{\mathrm{­}}$A/cm$^{2}$, which is smaller than that of the fin-type GaN JLFET, i.e., 9.72 ${\times}$ 10$^{\mathrm{\hbox{-}2}}$$_{\mathrm{­}}$A/cm$^{2}$. Thus, the vertical cylinder-type GaN JLFET demonstrated higher gate controllability than the vertical fin-type GaN JLFET.

Fig. 2(c) represents the BV curves of the vertical cylinder- and fin-type GaN JLFETs. The BV values of the two devices were 2,400 and 2,037 V at V$_{\mathrm{GS}}$ = 0 V, respectively. These results demonstrate a 17.8% increase in the BV and electrical performance of the vertical cylinder-type GaN JLFT compared with those of the vertical fin-type GaN JLFET. Next, we analyzed the electric-field distribution of the two devices, as shown in Fig. 5(a) and (b) at V$_{\mathrm{DS}}$ = 1,500 V. As shown, the vertical cylinder-type GaN JLFET has an evenly distributed electric field, whereas that of the fin-type GaN JLFET is concentrated in a corner ^[15]. Fig. 5(c) represents the peak point of the electric field of the two devices at the B-B’ cutline, which is the interface between the oxide and channel region at V$_{\mathrm{DS}}$ = 1,500 V. The electric field in the corner region is at its maximum for the two devices at 2.27 and 2.78 MV/cm, respectively.

These results indicate that the electric-field distribution is concentrated at the corner region of the vertical fin-type GaN JLFET. Thus, this device has a relatively larger value than the vertical cylinder-type device, and it consequently breaks down more easily. In addition, Fig. 6(a) and (b) shows the current density of the vertical cylinder- and fin-type GaN JLFETs, respectively. As shown in Fig. 6(a), the cross-sectional views at V$_{\mathrm{DS}}$ = 2,100 V for the vertical fin-type GaN JLFET demonstrate that the breakdown has already occurred, resulting in leakage- current flows. By contrast, Fig. 6(b) shows that the leakage current in the vertical cylinder-type GaN JLFET does not flow at V$_{\mathrm{DS}}$ = 2,100~V.

Fig. 2. (a) Linear and logarithmic transfer curves (ID–VGS); (b) output curves (ID–VDS); (c) BV curves of the vertical cylinder- and fin-type GaN JLFETs.

Fig. 3. Schematic of channel resistance (Rch) and total resistance (Rtotal) sum of Rdrift, Rn+, and Rsub of the vertical cylinder- and fin-type GaN JLFETs [9].

Fig. 4. (a) Channel of the vertical cylinder-type GaN JLFET at the off-state (VGS = 0 V); (b) Energy-band diagram of the vertical cylinder-type GaN JLFET at A–A’; (c) Channel of the vertical fin-type GaN JLFET at the off-state (VGS = 0 V); (d) Energy-band diagram of the vertical fin-type GaN JLFET at A–A’.

Fig. 5. Channel regions of the (a) vertical cylinder-type GaN JLFET; (b) vertical fin-type GaN JLFET at VDS = 1,500 V; (c) The peak points of the electric field of the GaN JLFETs at the B–B’ cutline.

Fig. 6. Current densities of the (a) vertical fin-type GaN JLFET; (b) vertical cylinder-type GaN JLFETs at VDS = 2,100 V.

IV. CONCLUSIONS

This study analyzed the performances of the vertical cylinder- and fin-type GaN JLFETs in terms of the GaN-on-GaN substrate using 3D TCAD simulations. The substrate area of both these power transistors was valued equally at 250 ${\mu}$m$^{2}$. Accordingly, the I$_{\mathrm{on}}$ of the vertical cylinder- and fin-type JLFETs was obtained as 6.45 and 5.63 kA/cm$^{2}$, respectively, showing a 15.59% increase. Moreover, the corresponding I$_{\mathrm{off}}$ values of these devices were obtained as 2.51 ${\times}$ 10$^{\mathrm{\hbox{-}10}}$ and 9.72 ${\times}$ 10$^{\mathrm{\hbox{-}2}}$ A/cm$^{2}$, respectively, and the I$_{\mathrm{off}}$ ratio of the two devices was 2.58 ${\times}$ 10$^{9}$. The results showed that the vertical cylinder-type GaN JLFET possesses higher turn-off and gate controllability than the fin-type device. This is because the device has a GAA structure, which can easily achieve full depletion if the gate controllability is enhanced. Therefore, the current can be easily controlled in the cylinder-type device. Thus, the leakage current in this device is relatively smaller and the BV is larger than that of the fin-type device. In conclusion, the proposed vertical cylinder-type GaN JLFET has the advantage of on-off characteristics, suggesting future research direction in the design of high-performance vertical GaN power transistors.