김순용
(Soon-Yong Kim)
†iD
JoshiSaurabh Suredra1
KimSoomin2
KimChang-Hyun1
ChoSeongjae2,*
-
(Department of Electronic Engineering, Gachon University, Sujeong-gu, Seongnam-si,
Gyeonggi-do 13120, Korea)
-
(Department of Electronic and Electrical Engineering, Ewha Womans University, 52 Ewhayeodae-gil,
Seodaemun-gu, Seoul 03760, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Resistive-switching random-access memory (ReRAM), hafnium dioxide, circuit and system simulation, multi-level conductance, compact model
I. INTRODUCTION
As the development of information and communication technologies such as internet
of things (IoT), artificial intelligence (AI), and machine learning (ML) with big
data, high-speed and energy-efficient computing architecture have been actively exploited.
When considering the nonvolatile memory (NVM) components which play crucial roles
as synaptic device as well as stand-alone memory unit, resistive-switching random-access
memory (ReRAM) is regarded as one of the most promising next-generation NVMs owing
to its high device scalability, fast switching speed, and stack array processing viability.
Along with the stand-alone memory application, ReRAM is frequently considered as the
synaptic device in the neuromorphic computing, more hardware-driven AI, which usually
calls for multi-level weight tunability (electrical conductance states) helped by
optimally designed conductance update algorithms [1]. However, circuit and system-level design lack of accurate compact ReRAM models describing
the device behaviors. In order to reflect the empirically observed resistive-switching
characteristics, several compact models have been constructed [2-4]. The majority of the past works have been dedicated to exaggeratedly simplified models
solely based on filament growth with full predictability at room temperature. For
higher accuracy, stochastic filament growths and temperature dependence can be further
implanted in the model. By preparing an advanced ReRAM model, reliability in circuit
and system designs would be substantially enhanced [5,6]. Efforts were dedicated to more dynamic physics-based compact models, in consideration
of thermal effects, time-dependent conduction change, and stochastic behaviors of
ReRAM, in a few works [7-9]. However, high computational expenses in terms of time and cost need to be considered
when the circuit and system-level simulations based on ReRAM cells are performed.
In this work, a compact ReRAM model with higher compactness and accuracy has been
developed utilizing Verilog-A and HSPICE in cooperation. As the result, more exact
portrayals of spatial and transient growth progress of the conductive filament have
been achieved. Further, the dependency of conductance change on the level of compliance
current has been reflected.
II. PHYSICS AND PARAMETERS
The process of conducting filament (CF) construction can be schematically illustrated
as shown in Fig. 1(a) through (e). The switching material was assumed to be HfO$_{2}$ in compact modeling.
HfO$_{2}$ has been already confirmed with its Si compatibility and brought into the
massive production in logic semiconductor technologies [10]. It is also found in the researches on ferroelectric devices in recent times [11]. For these reasons, introducing HfO$_{2}$ into the RRAM application would make the
over process integration more Si-friendly and provide higher viability of integration
with CMOS circuits and other memory technologies on a single chip [12]. In the model, the CF growth is depicted by the change in length of the CF determined
by the biasing condition between set and reset operations. It is known that the construction
of a CF results from the migration of oxygen ions, vacancy movements, and carrier
transports in the oxide-based ReRAMs. One or more conduction mechanisms for the carrier
transport across the switching layer can attribute to the conduction current in low-resistance
state (LRS) and high-resistance state (HRS). At the same time, the dependence of conduction
current on geometric effect, the filament length (or equivalently the oxide barrier
length), should be considered in modeling. The barrier length can be expressed as
a function of electric field between the top electrode (TE) and the top of the tip
end. It is universal to understand which conduction mechanism might have the predominance
in determining the conduction current by having a close look into the formulation
between the electric field and conduction current. A simple model in Fig. 2 can be the preliminary frame, in which TE and bottom electrode (BE) resistances,
switching resistance, and switching layer capacitance are considered. Specifically,
The TE and BE metals are TiN and Pt, respectively. The resistances of these electrode
metals used in the simulation works are 5 ${\times}$ 10$^{-4}$ ${\Omega}$ and 2.1
${\times}$ 10$^{-3}$ ${\Omega}$, respectively, and the values were brought from the
previous literature [5-7].
Fig. 1. Schematics of a ReRAM cell under different bias conditions: (a) Before; (b) after forming operations. The blue cylinder indicates the conductive filament; (c) Reset operation partially oxidizes the CF creating a barrier (orange cylinder). The barrier length increases as the magnitude of bias gets larger over a RESET operation in (d) and (e).
Fig. 2. A widely used simple equivalent circuit of ReRAM cell composed of resistors and a single capacitor.
III. RESULTS AND DISCUSSION
A. Forming Operation and Current Compliance
Forming operation is attributed by controlled breakdown of the switching layer, which
is usually accomplished by applying a high enough positive voltage while forcing a
particular level of compliance current I$_{\mathrm{C}}$. The forming operation can
be explained by a process in the loop of feedback between temperature and field effects
causing the creation of CFs in the switching layer. The path for vacancy movements
is prepared in this manner, through which the set and reset operations are realized.
The read current after a set operation, LRS current, can be converted to LRS resistance
depending on cases, by simply dividing the read voltage (inference voltage in the
application of ReRAM cell as a synaptic device) by the LRS current. Further, the inverse
of LRS resistance, electrical conductance, can be translated as the synaptic weight.
In practical operation of ReRAM cells, limit in conduction current needs to be put.
Otherwise, it becomes very probable to observe failure in reset operation due to the
CFs excessively thickened by a high LRS current [13-19].
B. Reset Operation and Filament Dynamics
The reset operation, sensible by the change in resistance from LRS to HRS, is described
by a dynamic fractional oxidation of the CF due to field and temperature-driven movement
of oxygen atoms and their recombination with the metallic species (Hf in this work).
Trap-assisted tunneling (TAT) of charges can be found in the current conduction across
the barrier formed in the CF [17]. For a reset operation, a large enough negative voltage is applied on the TE with
regard to BE in the ReRAM cell. Gap distance (g) between the filament tip and the
electrode on the other side can be set as a dependent variable determined by external
electric field, which eventually determines the cell conductivity. The speed of change
in gap distance, or equivalently, growth speed of the CF can be described by a closed-form
equation, Eq. (1), as follows:
Here, E$_{a}$ is the activation energy for vacancy generation, t$_{ox}$ is the switching
layer (metal oxide) thickness, a$_{0}$ is the distance between hopping sites, and
V is the applied voltage between TE and BE. ${\gamma}$ is the local field enhancement
factor accounted for polarizability of the switching layer dielectric and can be modeled
as a function of gap distance g as follows in Eq. (2).
where ${\gamma}$$_{0}$ and ${\beta}$ are fitting parameters. In particular, ${\beta}$
reflects the gradual nature of reset process. Accuracy and reality can be further
expected by plugging a temperature function T into Eq. (1). By introducing a function T in Eq. (3), dependences on fluctuation in temperature, ${\delta}g$(T), and conduction current
at a specific time are considered for more precise calculation of dg/dt as a function
of T, I, V, and time, concurrently.
Here, I is the current through the ReRAM cell at a moment and R$_{\mathrm{th}}$ is
the equivalent resistance. Eqs. (2) and (3) are rearranged in Eq. (1) to keep away from utilization of various conditions, which lifts up the convergence
problems and greatly reduces total time in executing the Verilog-A codes. The gap
distance g is calculated by considering electric field, temperature-dependent oxygen
migration, and local temperature. The current flowing through an ReRAM cell can be
formulated in relations with V and g as Eq. (4). g$_{0}$, ${\alpha}$, and V$_{0}$ can be extracted in fitting the modeled current
to the experimentally measured value.
Table 1 summarizes the values of the primary parameters making up Eqs. (2) through (4), which have been adopted in compact modeling. The reference current I$_{0}$ of 1
A in Table 1 is surely an excessively large quantity but it makes the control over ${\alpha}$
more easily recognizable. ${\alpha}$ plays a role of scaling I$_{0}$ down to a modeled
current to a realistic value in consideration of the cell area, by which a rather
imaginary number of I$_{0}$ is altered a practical one. Fig. 3 shows the I-V curve from the developed compact model with I$_{\mathrm{C}}$ = 1 μA.
The modeled HfO$_{2}$ ReRAM cell clearly exhibits bipolar switching behaviors with
the set operation voltage at 1 V and the reset one at -1.2 V, which demonstrates low-voltage
operation capability. These results show the coherence with those obtained in an earlier
literature on the ReRAM device with the same material stack [14].
Fig. 4 shows that the weight tunability has been also modeled altering the compliance current.
Controlling the compliance current can be presumed to be realized by either width
or gate voltage control over the transistors at the bitline ends in the practical
sense. Further reduction in power consumption can be schemed with the help of optimal
structure design with adequately working scalability based on the lumped equations
in the mode. The constructed model can be transplanted into the higher-level integrated
circuit and system designs toward the advanced computing architecture embedding the
ReRAM cell array.
I$_{0}$, g$_{0}$, V$_{0}$, ${\upsilon}$$_{0}$, ${\gamma}$$_{0}$, and ${\beta}$ are
the practical parameters that effectively fit the modeled curve to the median of switching
behaviors of the measured ReRAM cell. Fig. 5(a) through (e) systemically demonstrates the effects of individual fitting parameters
on DC switching I-V characteristics of the ReRAM cell to be modeled. I$_{0}$, g$_{0}$,
and V$_{0}$ dominate the nonlinearity in the I-V curves as can be inferred by Fig. 5(a), (c), and (e). V$_{0}$ depicts the nonlinearity in the resistance curve more specifically.
I$_{0}$ mainly shifts the curve to different current levels. g$_{0}$ has the major
controllability over the set operation voltage shift as shown in Fig. 5(b). ${\upsilon}$$_{0}$, ${\gamma}$$_{0}$, and ${\beta}$ are correlated with the process
of filament growth, or change in gap distance g. In particular, ${\upsilon}$$_{0}$
and ${\gamma}$$_{0}$ determine the voltage where the gap starts to grow. ${\upsilon}$$_{0}$
mainly changes the reset voltage at the knee point, while ${\gamma}$$_{0}$ has an
effect of adjusting set voltage. ${\beta}$ modulates the slope in the reset operation
as shown in Fig. 5(d). Fig. 6 depicts the displacement current in the modeled HfO$_{2}$ ReRAM cell as a function
of pulse rising time. Rising time of the input pulse in operating an ReRAM device
is one of the important control variables regarding operation speed and device reliability.
There can be a huge amount of surge displacement current in the short rising time
regime as can be implied by Fig. 5. The displacement current stimulated by a pulse with a short rising time originates
from the capacitive component depicted in Fig. 2, which exists in the actual ReRAM cell due to the switching dielectric layer, not
just as a modeling component [15]. Fig. 6 provides a guideline for optimally shaping the operation voltage pulse.
Table 1. Simulation parameters and the extracted coefficients
Parameters
|
Values
|
Ea
|
0.6 eV
|
a0
|
0.25 nm
|
tox
|
8 nm
|
I0
|
1 A
|
g0
|
0.25 nm
|
V0
|
0.25 V
|
Fig. 3. DC I-V characteristics of a HfO2ReRAM cell showing typical bipolar switching behaviors.
Fig. 4. Weight tunability by compliance with current control.
Fig. 5. Dependency of I-V characteristics of a HfO2ReRAM cell on model parameters: (a) LRS current levels at different I0’s in the positive bias region; (b) Change in set voltage by controlling γ0; (c) LRS current levels by changing g0 in the negative bias region; (d) Reset operation slope in the effect of β; (e) I-V curve slope in the positive bias region depending on V0.
Fig. 6. Displacement current in the modeled HfO2ReRAM cell as a function of rising time of a pulse.
V. CONCLUSION
In this work, we have presented a more accurate compact model of an ReRAM cell with
a HfO$_{2}$ switching layer. For higher accuracy and credibility of the model, stochastic
device characteristic deviations subordinate to temperature change has been considered
in describing the filament growth. Bipolar resistive-switching characteristics have
been plausibly reproduced by the developed model in comparison with the measurement
results. Also, it has been affirmed that multiple conductance levels can be obtained
from the ReRAM model by identifying the deciding parameters. The weight tunability
can be put in conjunction with pulse operation schemes for potentiation and depression
of a synaptic device as a future task. The more accurate and compact model will play
a crucial role as a pivotal part in higher-level simulations and framework tasks for
faster design of integrated circuits and systems embedding a large ReRAM array toward
the neuromorphic and processing-in-memory (PIM) applications as well as high-density
memory product.
ACKNOWLEDGMENTS
This work was supported by National Research Foundation of Korea (NRF) funded
by the Ministry of Science and ICT of Korea (MSIT) under the Grant No. 2021M3F3A2A01037927
and 2021M3H4A6A01048300. Also, this work was supported by IC Design Education Center
(IDEC) for simulation tools.
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Saurabh Suredra Joshi received the B.Tech. degree in electronics and telecommunication
engineering at Sant Gadge Baba Amravati University, Maharashtra, India, in 2014 and
M.Tech. degree in nanotechnology at Vellore Institute of Technology, Tamilnadu, India,
in 2016. He is currently pursuing the Ph.D. degree at Gachon University, Seongnam,
South Korea. His research interests include design and simulation of next-generation
semiconductor such as ReRAM and organic thin-film transistors (OFETs).
Soomin Kim received the B.S. degress in electronics and electrical engineering
from Ewha Womans University, Seoul, Korea, in 2023. She is currently pursuing the
M.S. degree at Ewha Womans University. Her current research interests include nanoscale
CMOS devices, low-power synaptic device, and neuron circuits for neuromorphic system.
Chang-Hyun Kim received B.Sc in information display from Kyung Hee University,
Korea, in 2007. He received M.Sc. in technological innovation engineering in 2010
and Ph.D. in physics in 2013, both from the Ecole Polytechnique, France. He held postdoctoral
fellowships at Columbia University, USA, the French National Centre for Scientific
Research (CNRS), and Gwangju Institute of Science and Technology (GIST), Korea, prior
to joining the faculty of Gachon Univeristy, Korea, in 2018. He is currenly an Associate
Professor of Electronic Engineering at Gachon Univeristy. He is a Senior Member of
IEEE. His group develops analytic tools and experimental methods for the design and
implementation of multifunctional organic and hybrid thin-film electronic devices.
Seongjae Cho received the B.S. and the Ph.D. degrees in electrical engineering
from Seoul National University, Seoul, Korea, in 2004 and 2010, respectively. He worked
as an Exchange Researcher at the National Institute of Advanced Industrial Science
and Technology (AIST), Tsukuba, Japan, in 2009. He worked as a Postdoctoral Researcher
at Seoul National University in 2010 and at Stanford University, Palo Alto, CA, from
2010 to 2013. Also, he worked as a faculty member at the Department of Electronic
Engineering, Gachon University, from 2013 to 2023. He is currently working as an Associate
Professor at the Department of Electronic and Electrical Engineering, Ewha Womans
University, Seoul, Korea, from 2023. His current research interests include emerging
memory technologies, advanced nanoscale CMOS devices and process integration, group-IV
photonic devices, low-power synaptic devices and neuron circuits for neuromorphic
and memory-centric processor technologies. He is a Senior Member of IEEE and a Lifetime
Member of IEIE. He was the recipient of the Minister’s Award from the Ministry of
Science and ICT of Korea (MSIT) in 2021.