I. INTRODUCTION

Low-dropout (LDO) regulators are a type of voltage regulator that is frequently used in contemporary electronic devices to provide a precise and stable DC supply voltage. In applications that require a low output voltage, a low dropout voltage, and low output noise, LDO regulators are preferred over other voltage regulators, such as linear regulators and switch-mode regulators ^[1].

Power supply rejection ratio(PSRR) is an important performance parameter that measures the ability to maintain a stable output voltage in the presence of power supply noise. Due to the output conductance of pass transistor and the bandwidth limitations of feedback path, the conventional LDO has low PSRR performance at high frequencies. The feedforward method overcomes this restriction by lessening the impact of the power supply noise by adding a compensating signal to the output voltage ^[2]. However, the addition of these extra circuits increases the number of dominant poles and causes the non-dominant pole to pull into the low frequency when the load current is small, resulting in stability problems ^[3]. Using a zero generator and the current sensing of the load current described in this paper, it can be efficiently compensated.

This study proposed the current sensing method to improve the stability of LDO regulators and feedforward techniques to enhance PSRR compared to conventional LDO. This paper is organized as follows. Section II presents the proposed LDO and Section III explains the interpretation of PSRR and stability. Section IV discusses simulation results. Finally, the conclusion is given in Section V.

II. ARCHITECTURE

Fig. 1 shows the overall architecture of the proposed LDO. The error amplifier, feedforward amplifier, and summing stage are referred to as EA, FFA, and SUM, respectively. In addition to the current feedback loop, a feedforward path has been added for quick compensation. Through the proposed compensation technique, it plays an auxiliary role in increasing the PSRR. The zero is generated by the NMOS transistor to ensure the stability of LDO. Through the current sensing block, the load current value enters the input of the NMOS transistor gate (e.g., M$_{\mathrm{27,}}$M$_{28}$), where the two zero positions change dynamically with variations in the load current value ^[4].

Fig. 2 shows the schematic overall block excluding current sensing. The transistors M$_{1}$-M$_{6}$ that make up the EA are intended to function as the NMOS transistor input OTA. By using the NMOS transistor input OTA structure, a faster feedback speed is ensured. The transistors M$_{7}$-M$_{14}$ composed in the FFA are designed with a two-stage amplifier to achieve a high gain. The feedforward path and the feedback-regulating loop at the pass transistor's gate (i.e., M$_{\mathrm{P}}$) are integrated by the summing stage. It also provides a path to secure higher loop gain values compared to conventional LDO. This serves as an important intermediate step for achieving a high PSRR value. The reference voltages V$_{\mathrm{REF}}$ and V$_{\mathrm{REFZ}}$are externally provided as bias voltages, and the PMOS transistors are used in l$_{1}$ and l$_{2}$ to regulate the current flow for the current mirror.

Fig. 3 shows the overall current sensing schematic. M$_{20}$-M$_{24}$ is designed to have a structure with a relatively large width of transistor for accurate current sensing. This design choice facilitates a positive feedback mechanism, enhancing the precision of current sensing even in the presence of minute current variations. Then, to more precisely modify the input values of M$_{27}$ and M$_{28}$, which serve as the resistance, use M$_{25}$ and M$_{26}$.

Fig. 1. Proposed feedforward LDO block diagram.

Fig. 2. Schematic of the proposed feedforward LDO.

Fig. 3. Schematic of the current sensing.

III. ANALYSIS OF THE PROPOSED LDO

1. PSRR Analysis

This section analyzes the PSRR of conventional LDO in ^[2] and the proposed LDO at high frequency. Fig. 4 shows the block diagram of proposed LDO block with ripple cancellation paths as well as the paths where ripples are generated assuming conventional LDO. In the conventional LDO, paths 1 to 4 are the main sources of output ripple voltage. However, the domain pole of the error amplifier of paths 3 and 4 converges to zero at high frequencies. As a result, in cases of high frequency, path 3 and 4's influence may be disregarded. The transfer function for paths 1 and 2 is given by

(1)

$\frac{V_{OUT}}{V_{IN}}\left(s\right)=\frac{1+M_{P,{g_{m}}}\cdot M_{P,{r_{ds}}}}{1+\frac{M_{P,{r_{ds}}}}{Z_{L}\left(s\right)}+\frac{M_{P,{r_{ds}}}}{R_{1}+R_{2}}+\frac{M_{P,{g_{m}}}\cdot M_{P,{r_{ds}}}\cdot A_{eo}\cdot R_{2}}{\left(R_{1}+R_{2}\right)\left(1+\frac{s}{w_{e}}\right)}} $

Z$_{\mathrm{L}}$, A$_{\mathrm{eo}}$, W$_{\mathrm{e}}$ are the impedance load of the load and the DC gain and dominant pole of the error amplifier, respectively. $M_{P,\,{g_{m}}}$ and $M_{P,\,{r_{ds}}}$ are the transconductance and channel resistance of the pass transistor. As the equation shows, the PSRR depends on the feedback gain. As frequency increases, the dominant pole of the error amplifier reduces the feedback gain, which in turn causes the PSRR to degrade.

To overcome this limitation, the feedforward path compensation is added as shown in Fig. 4 and 5 shows the mathematical block diagram that expresses these compensation effects. The following equation shows how the input to output transfer gain is determined.

(2)

$\frac{V_{OUT}}{V_{IN}}\left(s\right)=\frac{1+M_{P,{g_{m}}}\cdot M_{P,{r_{ds}}}\left[1-H_{ff}\left(s\right)\right]}{1+\frac{M_{P,{r_{ds}}}}{Z_{L}\left(s\right)}+\frac{M_{P,{r_{ds}}}}{R_{1}+R_{2}}+\frac{M_{P,{g_{m}}}\cdot M_{P,{r_{ds}}}\cdot A_{eo}\cdot R_{2}}{\left(R_{1}+R_{2}\right)\left(1+\frac{s}{w_{e}}\right)}} $

Eq. (2) is set to zero to eliminate the ripples at the output. H$_{\mathrm{ff}}$(s) is the feedforward block`s transfer function and can be obtained by the following equation.

(3)

$H_{ff}\left(s\right)=1+\frac{1}{M_{P,{g_{m}}}\cdot M_{P,{r_{ds}}}} $

When the gain of the feedforward amplifier is as shown in Eq. (3), the PSRR significantly increases. However, the feedback gain in Paths 1 and 2, as well as the power supply regulation ratio of the error amplifier and the bandgap circuit in Paths 3 and 4, are the parameters that affect PSRR in the low-frequency region. Thus, this needs to be taken into consideration when designing it.

Fig. 4. Ripple paths from input to output in conventional LDO and feedforward cancellation paths in proposed LDO.

Fig. 5. Mathematical model of the LDO.

2. Stability Analysis

As shown in Fig. 6(a), the proposed LDO without current sensing changes only the location of the dominant pole whenever the size of the load changes, and it makes difficult to secure stability flexibly. Because the zero value cannot shift smoothly as the load changes if general resistance is used without utilizing zero using current sensing and transistor. To overcome this stability issue, the proposed LDO is designed with the zero generator that creates the zero through current sensing at the load current. As a result, as shown in Fig. 6(b), the pole and zero move to ensure more stable stability than the conventional LDO when the value of the load current changes.

Fig. 6. Conceptual analysis of frequency response with different load conditions: (a) Proposed LDO without current sensing; (b) Proposed LDO.

IV. SIMULATION RESULTS

The 28 nm CMOS process was used to implement the proposed LDO that controls the output at 1 V from a 1.2~V supply. Fig. 7 shows gain and phase margin when the I$_{\mathrm{LOAD}}$ of conventional LDO and proposed LDO is 1~mA and 10 mA, respectively. In proposed LDO, the simulated phase margin for the cases when I$_{\mathrm{LOAD}}$ = 1 mA and I$_{\mathrm{LOAD}}$ = 10 mA are 64˚ and 68˚, respectively.

Fig. 8 compares the PSRR with and without feedforward. LDO without a feedforward amplifier has -16 dB of PSRR at the low frequency. However, the proposed LDO with a feedforward amplifier makes the improvement to have -69 dB of PSRR at the low frequency. Fig. 9 shows the change in quiescent current over the load current range. When the load current changes from 0 mA to 10 mA, the total quiescent current changes between 16.1 $\mu$A and 32 $\mu$A. The peak current efficiency is 99.7% at 10 mA.

Fig. 10 shows the V$_{\mathrm{OUT}}$results when the I$_{\mathrm{LOAD}}$ value changes from 1 mA to 10 mA with rise and fall times of 10 ns. The overshoot value is 1.83 mV when I$_{\mathrm{LOAD}}$ decreases from 10 mA to 1 mA. On the other hand, the undershoot value is 4.68 mV when I$_{\mathrm{LOAD}}$ increases from 1~mA to 10 mA. Also, during the upper mentioned transition condition, the settling time is 0.177 ${\mu}$s with 3% accuracy. A comparison of the performance with other works is shown in Table 1. Among the reference papers included in Table 1, the proposed LDO shows the lowest PSRR. In order to compare the transient response of various LDOs, a figure of merit (FOM) = T$_{\mathrm{r}}$(I$_{\mathrm{q}}$/I$_{\mathrm{L,max­}}$) ^[12] is used to figure out the trade-offs between the maximum load current I$_{\mathrm{L,max}}$, the quiescent current I$_{\mathrm{q}}$ and the response time T$_{\mathrm{r}}$.

Fig. 7. AC simulation results: (a) Conventional LDO; (b) Proposed LDO.

Fig. 8. Results of simulation PSRR from LDO.

Fig. 9. Results of simulation quiescent current under different load currents.

Fig. 10. Simulated load transient response.

Table 1. Performance comparison

V. CONCLUSIONS

In this paper, a new structure of the feedforward method is proposed to increase PSRR. A supporting role for the FFA block in reducing the V$_{OUT}$ ripple. Additionally, by using current sensing to create a zero generator, a stable PM for the overall stability of LDO is established. The simulated PSRR has a -38 dB enhancement at 100 kHz when compared to an LDO with no feed-forward amplifier. Finally, the proposed LDO shows small overshoots and undershoots and demonstrates the outcome of maintaining a constant output voltage.