I. INTRODUCTION

Recently, Tunnel Field-Effect Transistors (TFETs) have been studied as promising alternatives to metal-oxide-semiconductor field-effect transistors (MOSFETs) ^[1-6], particularly for very low-power application. Based on carrier injection through band-to-band tunneling (BTBT), significant progress has been made in achieving a subthreshold swing (SS) of less than 60 mV/dec at room temperature (RT) and minimizing low-level off-state current (I_off). Nevertheless, in contrast to MOSFETs, TFETs face a challenging issue with low on-state current (I_on). To address this, a high-${\kappa}$ / metal gate (HKMG) materials have been adopted instead of polysilicon gate. The HKMG, capable of reducing gate leakage and ensuring high channel controllability, has shown promise in improving TFET performance ^[7-10].

Despite advancements in I_on characteristics, Titanium Nitride (TiN), a common HKMG material, introduces work function variation (WFV). Sputtered TiN tends to crystallize predominantly in <200> (60%) and <111> (40%), corresponding to WFs 4.6 eV and 4.4 eV respectively. This non-uniformity in metal gates contributes to WFV, influencing TFET current variations ^[11-13].

Therefore, when implementing the TFETs into real complementary metal-oxide-semiconductor (CMOS) circuits, it is essential to examine electrical performance variations in relation to WFV. However, studies addressing this issue have been limited. Some researchers have proposed nanowire TFETs as the gate of nanowire TFET effectively reduces WFV by minimizing the affected channel area ^[14-16]. Despite efforts to improve this aspect, WFV still persists. Consequently, identifying the primary cause has become crucial for reducing or eliminating WFV ^[17].

The primary objective of this study is to establish causal relationships using a machine learning (ML) approach ^[18-20]. ML facilitates a comprehensive analysis of TFETs even in the absence of complete WFV data samples. It allows for predictions by adjusting output parameters and constructing a model that captures variations in electrical operations associated with WFV, combining the variation of current.

ML allows to identify the cause with a limited dataset. However, once relevant parameters are identified, ML models need optimization by pinpointing exceptional cases that were not part of the training data. Models, trained on less data tend to exhibit low R² value for parameters with less relevance. Therefore, it was necessary to reduce sensitivity to identify parameters that have a direct impact.

Transistor samples have been verified using technology computer-aided design (TCAD) and simulations were conducted using Synopsys Sentauraus ^[20,21]. With relevant parameters, ML predicts exceptional situations by different WF in each area. In Section 2, we delve into the valuable output parameters (e.g., SS, Threshold voltage (V_th), minimum current (I_min), turn-on voltage (V_on)) influenced by WFV. Section 3 outlines the most relevant input parameter identified by ML. Subsequently, in Section 4, the ML model is constructed using data highly dependent on Drain Voltage (V_d). Finally, Section 5 presents predictions for exceptional situations.

II. DEVICE DESIGN AND METHODOLOGY

In Fig. 1(a), a bird’s eye view of a nanowire TFET is presented. The simulation, conducted using TCAD, features a gate oxide thickness (T_ox) of 1 nm with SiO₂. Arsenic and boron are used as the dopant atoms for n-type and p-type doping, respectively. The structure of the TFET is p-i-n, with a TiN gate and a channel length of 20 nm. All simulations are performed at RT and the design parameters are summarized in Table 1. Fig. 1(b) displays a bird’s eye view of a WF randomized model, while Fig. 1(c) illustrates the Y-axis cross-section. The grain size of TiN is assumed to be an identical, forming a 5 ${\times}$ 5 nm² of square shape ^[22].

Fig. 1. (a) Bird’s eye view of nanowire TFET; (b) Structure having random WF on gate; (c) Y-axis cross section and divided gate area; (d) Z-axis cross section and divided gate area.

Fig. 1(d) shows Z-axis view, where the gate covering channel is divided into 8 areas that contact the oxide part. Given the 5 ${\times}$ 5 nm$^{2}$ square shape of the TiN grain, the gate area is further divided into 32 units. WFV for each gate area is randomly assigned, taking into account these probabilities.

A thousand structures were generated for ML, with 32 WF parameters extracted from each grain near the gate. Additionally, 16 parameters, including conduction band and valance band electron volt values at V_g = 0.5 V, V_g =1.5 V, were employed to describe the WFV profile in nanowire TFET in Fig. 2(a). The parameter mark points contact with the dotted line on the graph (0.025, 0.075, 0.125, 0.175 ${\mu}$m). In total, 48 parameters were used for input to train the ML model.

Fig. 2. (a) Energy band diagram atVg= 0.5 V andVg= 1.5 V; (b)Id-Vgcurve atVd= 1.0 V; (c) Summary of ML model; (d) Visualization of ML algorithm.

For the ouput, four parameters (SS, V_th, I_off, V_on) were extracted from the I_d-V_g curve in Fig. 2(b). This curve illustates current’s variation with gate voltage. I_min, the minimum current flowing through the device, is measured at the lowest value of drain current, marked by green circle. SS, the subthreshold swing, represents the slope with increasing current and is measured at the point where the current increases 100 times from I_min, indicated by the purple circle. V_on is the gate voltage value defining the on-state, measured when the drain current reaches 10^-15 A/${\mu}$m marked on the blue line. V_th, the voltage at which the device operates, is measured when the drain current reaches 10^-9 A/${\mu}$m indicated on the red line. Its distribution follows a Gaussian distribution due to randomized grain.

To design an ML algorithm and enable predictions, the process followed the four steps, as illustrated in Fig. 2(c):

Step 1: Split the data into training, testing, and validation sets.

Step 2: Construct an ML algorithm by training it with the designated data.

Step 3: Monitor the epoch and loss until the weights are optimized.

Step 4: Adjust or refine the neural network architecture as needed and deploy it accordingly.

Following the outlined procedure, thousands of data points were divided into the ratio of 8:1:1 for training, testing, and validation. The built-in ML algorithm utilized a dense layer structure of 48 - 32 - 16 - 4 ^[23]. MinMaxScaler was employed to normalize parameters, ensuring consistency with the formula (i.e., (X - X_min) / (X_max - X_min)). Categorical Cross-entropy served as the loss function for each dense layer in Fig. 2(d), while the Adaptive Moment Estimation (ADAM) optimizer was chosen for accurate error correction, with a learning rate (LR) set to 0.001 ^[24]. Fig. 3(a) depicts the loss of the ML model during the building process. The appropriate epoch, indicating the point at which the loss reaches 0.04136, was determined through the observation of loss size as the epoch increased. For quantitative correlation verification, R² values were extracted for various parameters. R² values, a statistical measure of fit, were checked for each parameter—SS (0.7738), V_th (0.9933), I_min (0.5608), and V_on (0.9938), as shown in Fig. 3(b).

Fig. 3. (a) Loss of ML model from each epoch; (b) R2value of each output parameters.

Comparing the R² values for each parameter reveals a strong correlation between WFV and V_th,, V_on, while the relationship with I_min and SS is less shown. V_th and V_on exhibit higher R² values than SS and I_min. With sufficient data, the model could approach an ideal state for predicting all parameters accurately.

III. FINDING THE DETAILED CAUSE

Building upon the findings in Section 2 regarding the association between WFV, V_on, and V_th, mitigating the impact on WFV has become a key focus. In TFET, V_on is influenced by a current at the point where BTBT is maximized. To identify a more valuable input parameter, it is essential to locate the area with maximized BTBT. In Fig. 1(c), the gate is segmented into four areas designated as gate 1, 2, 3, and 4 from the source (far right) of the structure. To assess the impact of each gate region on V_on using ML, two gates were grouped together. These groups of the gates served as the input for the ML model, and evaluating the R² value elucidates the correlation between V_on and the group.

Sixteen parameters from the gates and eight parameters from the conduction and valence bands in the energy diagram were selected as input, while two parameters (V_on, V_th) were designated as the output. The dense layer architecture was configured as 24 - 16 - 8 - 2, utilizing the ReLU function ^[25]. The ADAM optimizer was employed for precise error correction, with a learning rate set to 0.001.

The comparison of R² values among different gate groups revealed that gate 1 and gate 2 exhibit a substantial correlation with V_on, as depicted in Fig. 4(a). Notably, the group containing gate 2 demonstrated R² values consistently at or above 0.9, indicating a robust correlation with V_on. This outcome highlights the significant influence of gate 2 on V_on. Considering that a significant portion of current in TFET is attributed to BTBT, as illustrated in Fig. 4(b) for an approximate gate voltage (V_g = 0.5 V) estimating V_on, BTBT primarily occurs at gate 1 and gate 2. This method enables the identification of the relative area contributing to the effect. The results confirm that ML models can effectively discern causative factors, facilitating optimization by establishing associ ations with each parameter.

Fig. 4. (a) R2value of each gate areas; (b) Electron BTBT generation of channel and separated gate area.

IV. MULTIPLE CAUSES OF VARIATION

To validate the previously developed ML model, it is crucial to examine whether it accounts for various effects. In contrast to MOSFETs, TFETs have been shown to receive inversion carriers from the drain. This inversion charge inhibits channel band bending, a phenomenon influenced by randomly distributed metal grains in the gate ^[26]. Additionally, when the V_d is low, several additional phenomena come into play. These include ambipolar characteristics, directly influenced by BTBT, and super-linear onset, observable by examining ambipolar current (I_AMB), V_th, and V_on ^[27].

The ML model for this investigation derived input from the structure and energy diagram, similarly shown as in Section 2. However, the output parameters were derived from Fig. 5(a) (I_d-V_g curve when V_d = 0.1 V). The selected output parameters for the ML model were I_AMB, V_th, and V_on, with I_AMB measured when V_g = -1 V. The built model exhibited a high R² value for predictions at each parameter, as shown in Fig. 5(b)-(d). The R² values for each parameter— I_AMB (0.9901), V_th (0.9901), and V_on (0.9927)—demonstrate that the ML model can accurately predict various phenomena with a high level of confidence.

Fig. 5. (a)Id-Vgcurve of nanowire TFET atVd= 0.1 V; (b) R2value ofIAMB; (c) R2value ofVth; (d) R2value ofVon; (e) Number of 4.4-eV grains; (f) R2value of prediction ofVonand testVonof new 10 exceptional data.

V. PREDICTION OF EXCEPTIONAL SITUATION

While most device structures exhibit average performance, devices such as CMOS or static random access memory (SRAM) can face performance challenges in exceptional situations ^[28]. This paper leverages ML to predict and address such exceptional scenarios that deviate significantly from the norm. ML models, developed in Section 2 and Section 5, were trained using data from Fig. 5(e).

Each gate in the ML model comprises grains with a 40% probability, featuring 4.4-eV grains whereas typical structures consist of 12 to 13 (average of 12.678) grains. To simulate an exceptional situation, 10 new structures were created, each with a 75% probability of acquiring 4.4-eV grains. In the existing structures, several 4.4-eV grains were located at positions 26, 22, 24, 20, 27, 24, 24, 26, 20, and 26, typically situated in the red part of Fig. 5(e). These structures were not part of the ML model training.

To make predictions, the grains and energy diagram of the structures were normalized using MinMaxScaler, a process consistent with the existing ML model inputs. The prediction of the input and output of the ML model was also normalized. Comparing the predicted V_on with the actual results, a high R² value of 0.9927 was achieved [Fig. 5(f)]. This outcome demonstrates that the ML model can effectively predict various exceptional situations.

VI. CONCLUSIONS

This study proposes the optimization of the ML model to establish a correlation between WFV and the variation of V_on in TFETs. Through the optimization and analysis of the ML model, it becomes evident that TFET performance is more affected by the number of gate regions than by the entire grain structure of the gate. This implies that only a few grains exhibit a high correlation with TFET's V_on. The ML model, relying on diverse data and exhibiting a strong dependence on parameters like V_d, demonstrates the potential for identifying multiple influencing factors. Furthermore, the ML model predicts that a gate with a higher proportion of 4.4 eV WF is likely to provide insights into the underlying causes. Ultimately, the results indicate the potential for prediction and analysis in the semiconductor process or simulation, particularly with sufficient and diverse data.