I. INTRODUCTION

Interests in quantum computing are growing rapidly with the recent developments of quantum computers by giant IT companies like IBM, Google, Microsoft or Intel ^[1]. A qubit is the basic unit of information in a quantum computer. It can be implemented with various physical methods such as photons, ion traps, electron spins, etc. Semiconductor spin-qubits and superconducting qubits, which are solid-state qubits, have the advantage of upscaling by integrating multiple qubits ^[2,3]. Especially, a silicon spin-qubit in CMOS, a well-established industrial manufacturing process, is a promising technology for high quality qubits due to its high-yield and reproducibility. On top of that, the capability to co-integrate interface circuits to control the qubits should be an essential advantage for the realization a large scale QPU (Quantum Processing Unit).

In general, the solid qubits require a very large number of interconnections to be connected with external control devices because they must be located in a cooling device for a cryogenic temperature to maintain a quantum state ^[4]. The interconnections increase exponentially as the number of qubits increases. They occupy a lot of space in a cooling device while providing a heat flow path into the device. This method becomes difficult to apply in a real system as the degree of integration of qubits increases. Recently, many researches on cryo-CMOS technology have been actively conducted to implements a qubit control device in the form of CMOS integrated circuits and places them right next to qubits to solve the issue ^[4-6]. A more compact and reliable quantum computer would be achieved using the approach without the complex interconnections.

A spin qubit is formed when an individual electron resides on a quantum dot to which a magnetic field is applied. Many semiconductor qubits employ magnetic field for controls ^[7-9]. The control device would be affected by the magnetic field as it is placed closer to qubits in the form of an integrated circuit or integrated with qubits. The investigation on electrical characteristics of thin films and contacts in a CMOS process under a cryogenic temperature and high magnetic field environment will be a basis for the design and analysis of CMOS integrated circuits for quantum computing.

Most cryo-CMOS researches focused on low temperature characteristics only without considering the effect of magnetic fields. Shim reported CMOS diodes under cryogenic temperature and high magnetic field environment ^[10]. This paper investigates measured resistive characteristics of thin films and contact structures in a 90-nm CMOS process both under a low temperature and high magnetic field for the first time. This paper reports a sheet resistance of four thin films and contact resistance of two contacts in a CMOS process under the temperature of 300 K, 150 K, 77 K and 4.2 K and the magnetic field of 0 T, 2 T, 4 T and 6 T, respectively.

II. TEST STRUCTURES

Table 1 lists the test structures: four thin film structures (TF1-TF4) and two contact structures (CT1 and CT2) for sheet resistance (R_) measurement and contact resistance (R_C) measurement, respectively. The thin film includes silicide and non-silicide semiconductor along with a metal layer. The thickness of poly-silicon in TF1 and TF3 is 0.15 ${\mu}$m. The thickness of TF2 is 0.12 ${\mu}$m. TF4 is implemented with 0.25-${\mu}$m copper layer.

The contact structures include the metal-to-n+ (n-well contact; CT1) and metal-to-metal (CT2) contact, respectively. The area of CT1 and CT2 is 0.12${\times}$0.12 ${\mu}$m² and 0.14${\times}$0.14 ${\mu}$m², respectively. The metal in the contact structure is copper.

Fig. 1(a) shows a layout of Van der Paw (VDP) structure for the measurement of sheet resistance (R_) of TF2. Fig. 1(b) shows a layout of Cross Bridge Kelvin Resistor (CBKR) structure for the measurement of contact resistance (R_C) of CT2. The size of both structures is 300${\times}$300 ${\mu}$m². R_ and R_C is calculated from (1) and (2), respectively ^[11]. I_AB is the current through the pad A and B, while V_CD is the voltage between the pad C and D. V_EG is the voltage between the pad E and G, while I_FH is the current through the pad F and H.

Fig. 1. Layout of (a) VDP structure (TF2); (b) CBKR structure (CT2) for the measurement.

III. MEASUREMENT RESULTS

The measurement setup described in ^[10] is employed to implement the low temperature and high magnetic field environment. The Quantum Design PPMS (Physical Property Measurement System) provides the low-temperature and high-magnetic environment for the measurements. Fig. 2 shows an example of the measured I-V curve for the R_ measurement of the silicide poly-silicon thin film (TF3) at the varying temperature using a semiconductor parameter analyzer (HP 4155A) under no magnetic field. The plot clearly shows the high linearity of the I-V curve throughout the current range.

Fig. 2. I-V curve for the R measurement of the Silicide poly-silicon thin film (TF3) for the varying temperatures.

Table 2 shows the measured resistances (R_ or R_C) for the different temperatures under no magnetic field. The resistances are measured at different current levels and averaged over the current range. The Max. Dev. in the table indicates the maximum deviation (absolute value) from the average R_ or R_C throughout the current range. The measured resistance is almost constant (highly linear I-V curves) throughout the current range with the maximum deviation of 1.59% (TF4 at 4.2 K). It shows that the structures do not experience any non-linear phenomenon such as a localized self-heating issue within the current range ^[12].

1. Temperature Dependence

Fig. 3 shows the temperature dependence of R_ under no magnetic field. All layers show the decreasing R_ with the decreasing temperature. Fig. 4 shows the temperature dependence of normalized sheet resistance normalized to R_ at 300 K. A layer with a smaller sheet resistance shows larger temperature dependence. TF1 (Non-silicide poly-silicon) shows a constant sheet resistance of around 100 ${\Omega}$/} throughout the temperature range. TF3 (Silicide poly-silicon) and TF4 (Metal) exhibit a larger variation with a typical temperature dependence of a metal. The R_ of TF3 and TF4 drops by 64% and 89.5% at 4.2 K, respectively. The resistance of a metal increases linearly with temperature above about 15 K due to the increase of electron-phonon interaction. As the temperature is sufficiently reduced to freeze all the phonons, the resistance usually reaches a constant value, known as the residual resistivity due to the effect of impurities and crystal defects ^[13]. It is important to consider the large temperature dependence of the metallic thin films in the design of integrated circuits for a cryogenic operation.

Fig. 3. Sheet resistance of the thin film layers versus the temperature (No magnetic field).

Fig. 4. Normalized sheet resistance of the thin film layers versus the temperature (No magnetic field).

Fig. 5 shows the measured contact resistances versus temperature. Both contact resistances drop as the temperature decreases. CT1 (Metal-to-n+) shows a larger drop of 35% at 4.2 K. A consistent theoretical prediction was reported in ^[14] for a contact resistivity with a high surface doping concentration. The current transport across a metal-semiconductor contact can be explained by thermionic emission and tunneling ^[14]. The tunneling mechanism becomes dominant as the doping concentration of a semiconductor increases and as a temperature decreases ^[10]. CT2 (Metal-to-metal) shows a smaller drop of 23% with the temperature decrease, which is quite smaller than 89.5% of TF4 (Metal). This indicates that the contact resistance will become more significant part of interconnect resistances than metal line resistances at a cryogenic temperature. It should be noted that no obvious anomalous phenomena or impurity freeze-out in the resistances were observed down to 4.2 K. It appears to be no fundamental barrier to achieve low-resistance contacts for low temperature operations.

Fig. 5. Contact resistances versus the temperature (No magnetic field).

2. Magnetic Field Dependence

An electrical resistivity of some materials changes when an external magnetic field is applied, which is called magnetoresistance (MR) effect. MR ratio is given by (3) ^[15]. R(B) and R(0) is the resistance (V/I) at the magnetic field density of B and 0 T, respectively.

(3)

$ \mathrm{MR}\left(\% \right)=\frac{\mathrm{R}\left(\mathrm{B}\right)-\mathrm{R}\left(0\right)}{\mathrm{R}\left(0\right)}\times 100 $

To characterize the magnetoresistance at cryogenic temperatures, the test structures are characterized under the magnetic fields up to 6 T. The measurements are performed for the orthogonal field orientations, B_V and B_H, which is perpendicular (vertical) and parallel (horizontal) to the silicon substrate, respectively (Fig. 6) ^[10].

Fig. 6. Magnetic field orientations for the field dependence measurements of the test structures.

Table 3 shows the maximum magnetoresistance of the thin film and contact structures (except TF4 (Metal)) under the magnetic fields of 0 T, 2 T, 4 T, 6 T, respectively. No test structures in the table show a meaningful variation (less than 1%). Fig. 7(a) shows the measured MR of TF4 (Metal) versus the magnetic field. The MR increases as the magnetic field increases. Fig. 7(b) shows the measured MR of TF4 versus the temperature. The MR exponentially increases as the temperature decreases under a same magnetic field. A theoretical model estimates the magnetoresistance is quadratically proportional to both a mobility and magnetic field ^[15]. Since the mobility of a metal is inversely proportional to a temperature, the results are somewhat consistent with the theoretical estimation.

Fig. 7. (a) MR versus the magnetic fields; (b) MR versus the temperature for the metal thin film structure (TF4).

Slightly higher magnetoresistances are observed under the horizontal orientation at a same temperature and magnetic field. The MR of TF4 reaches the maximum value of 10.4% under 4.2 K and 6 T in the horizontal orientation (B_H).

Table 3. Maximum magnetoresistance (%) of the thin film and contact structures

Thin Film/ Contact	300 K (%)	150 K (%)	77 K (%)	4.2 K (%)
TF1	0.35	0.17	0.19	0.73
TF2	0.31	0.37	0.39	0.32
TF3	0.14	0.56	0.11	0.56
CT1	0.47	0.60	1.00	0.26
CT2	0.89	0.14	0.24	0.45

V. CONCLUSIONS

The paper reported the resistance characteristics of thin films and contacts in a CMOS process under cryogenic temperature and high magnetic field environment for the first time. All measured sheet resistances (TF1, TF2, TF3 and TF4) decrease as the temperature drops. The thin films with a higher sheet resistance have a higher temperature dependence. The measured contact resistances (CT1 and CT2) also decreased as the temperature drops. It is estimated that a metal-to-metal contact (CT2) resistance dominates the metal interconnect resistances as the temperature drops.

No thin film or contact structures showed a clear magnetoresistance except TF4 (Metal). The MR of TF4 increases with the magnetic field while exponentially decreasing as the temperature increases. Slightly higher magnetoresistances were observed under the horizontal magnetic field orientation than under the vertical one.

It should be noted that no obvious anomalous phenomena or impurity freeze-out were observed under the temperature down to 4.2 K and the magnetic field up to 6 T. It appears to be no fundamental barrier to employing the thin films and contacts in CMOS for low temperature and high magnetic operations.

The investigation in this paper will be a basis for the design and analysis of the CMOS integrated circuits for quantum computing. The measurement results will also provide helpful information for the design of CMOS integrated circuits for EPR (Electron Paramagnetic Resonance) spectroscopy or aerospace electronics operating under the similar extreme environment ^[16,17]. They could further help the development of more refined device models considering a wide range of temperature and magnetic field.