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  1. (Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul 03760, Republic of Korea)
  2. (Computer, Electrical and Mathematical Science and Engineering Divi- sion (CEMSE), King Abdullah University of Science and Technology (KAUST), Thuwal 23955, Saudi Arabia)



GeSn, group IV material, indirect-to-direct bandgap transition, in-volume biaxial strain, highfrequency performance

I. INTRODUCTION

Given the scaling limits of conventional Si CMOS technology, functional materials with high carrier mobilities are increasingly being introduced. Ge, in particular, has garnered significant attention due to its high compatibility with Si and superior carrier mobility compared to Si [1,2,3,4]. Incorporating Sn atoms into Ge creates the notable alloy, Ge${}_{1-x}$Sn${}_{x}$, which has the potential to drive the next generation of both electronic and photonic devices with high carrier mobility modulation and wide bandgap tunability [5,6,7,8]. This tunability not only allows control over the electrical bandgap magnitude but also facilitates the transition to a direct-bandgap material, a property not typically associated with conventional group-IV materials such as Si and Ge [9,10,11,12]. Consequently, Sn incorporation enhances the electrical and photonic properties of Ge${}_{1-x}$Sn${}_{x}$, making it suitable for low-power, high-speed electronic and photonic devices [13,14,15,16,17]. Due to the excellent properties of GeSn, studies on GeSn layer growth are also being actively conducted [18,19,20,21]. To achieve more accurate simulation results than previous studies, this work effectively couples the Perdew-Burke-Ernzerhof (PBE) and modified Becke-Johnson (mBJ) potential models for solids to characterize Ge${}_{1-x}$Sn${}_{x}$. A comprehensive analysis of material parameters was performed as a function of Sn fraction and in-volume biaxial strain. The latter part of this paper presents a systematic approach to device simulation (Silvaco ATLAS 2D with Deckbuild interface), applying the material parameters obtained from atomic-level simulations (Quantum Espresso). The study examines how primary DC parameters, such as $I_{\rm on}$ and $S$, and high-frequency performance depend on Sn fraction and in-volume biaxial stress. Notably, the cut-off frequency (${f}_{\rm T}$) does not exhibit a monotonic dependence on the magnitude of tensile strain in GeSn but instead shows a local maximum. The compressive strain increased ${f}_{\rm T}$, reaching a maximum of 120 GHz at 0.5% strain.

II. FIRST-PRINCIPLE SIMULATION STRATEGY

Full-potential and all-electron schemes with relativistic effects were considered in the first-principle simulation to achieve higher accuracy and credibility. A two-atom unit cell for the base structure was used to construct the supercell (SC) shown in Fig. 1. Sn atoms were then incorporated into the Ge SC to represent the alloy with a targeted Sn fraction. Volume optimization was performed using the PBE model for solids, ensuring minimum energy and zero pressure. The Sn fraction was controlled from 0% to 12.5%, confirming bandgap modulation, specifically the indirect-to-direct bandgap transition. Under these conditions, in-volume pressure was applied to the SCs as in-volume biaxial strain, varying the lattice constant from -2% (compressive strain) to +2% (tensile strain). Although this situation can be virtually manipulated, it can be realized by applying external stresses from materials with intentionally deposited thermal expansion coefficients during process integration. By varying the Sn fraction and in-volume biaxial strain, 15 distinct SC models were constructed, and the mBJ potential models were applied to obtain more realistic energy bandgap values at non-zero temperatures.

Fig. 1. 16-atom Ge supercell comprising 2-atom unit cells used for ab initio calculations.

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III. RESULTS AND DISCUSSION

A. Material Simulation Results

Fig. 2 shows a total of 15 E-k band diagrams as a function of Sn fraction x and degrees of stress directions. The Sn fraction increases along the vertical axis from 0.000 to 0.1250, while the stress varies along the horizontal axis from -2% to +2%. The color and point size represent the Bloch spectral weights, which are determined by both the degeneracy of the allowed quantum states and the cumulative effects of the corresponding Bloch characteristics on the electron potential energy. Fig. 3 shows the energy levels of Ge${}_{0.937}$Sn${}_{0.063}$ and Ge${}_{0.875}$Sn${}_{0.125}$ at the L ($E_{\rm L}$), $\Gamma$ ($E_{\mathrm{\Gamma }}$), $\Delta$ ($E_{\mathrm{\Delta }}$) valleys; the heavy-hole and light-hole bands, along with the spin-orbit band, are also depicted. As the Sn fraction and external tensile strain increase, the bandgap energy becomes narrow. The indirect-to-direct bandgap transition occurred at approximately 0.581% compressive strain for Ge${}_{0.937}$Sn${}_{0.063}$, as shown in Fig. 3(a), and the direct-to-indirect bandgap transition occurred at approximately 0.778% tensile strain for Ge${}_{0.875}$Sn${}_{0.125}$, as shown in Fig. 3(b). The energy bandgap in the $\Gamma$ valley decreasesmore rapidly compared to those in the L and $\Delta$ valleys, leading to the indirect-to-direct bandgap transition. Even a small in-volume tensile strain, as small as 1%, induced a bandgap transition in Ge${}_{0.875}$Sn${}_{0.125}$. The electron affinity rapidly increases after the transition to a direct bandgap, as the $\Gamma$ valley lowers faster than the L valley, as shown in Fig. 4. With an increase in Sn fraction, the bandgap energy and effective DOS values decrease sharply, as shown in Fig. 5. All extracted and calculated parameters representing the material characteristics at various Sn fractions and strain conditions were then fed into the device simulations for the design of the GeSn ${n}$-type metal-oxide-semiconductor field-effect transistor (NMOFSET) design.

Fig. 2. E-$k$ diagram of Ge${}_{1-x}$Sn$_{x}$ as a function of Sn fraction ${x}$ and in volume biaxial strain.

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Fig. 3. Energy levels and bandgap transition as a function of the in-volume strain (a) Ge${}_{0.937}$Sn${}_{0.063}$ and (b) Ge${}_{0.875}$Sn${}_{0.125}$.

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Fig. 4. Electron affinity of Ge${}_{1-x}$Sn$_{x}$ as a function of in-volume biaxial strain and Sn fraction.

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Fig. 5. Bandgap energy of Ge${}_{1-x}$Sn$_{x}$ as a function of in-volume biaxial strain and Sn fraction.

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B. Device Simulation Results

As recent researches have demonstrated, studies on the design and fabrication of GeSn-based devices are increasingly important, emphasizing the importance of utilizing the excellent properties of GeSn for various electronic device applications [22,23,24,25]. To achieve this, the growth of high-quality single-crystalline GeSn on silicon platforms is crucial, as it ensures compatibility with existing Si-based technologies and enables practical device fabrication [26,27,28,29]. Most previous studies have focused on the application of Ge${}_{1-x}$Sn$_{x}$ to $p$-type MOSFETs, which typically exhibit a lower off-state current (${I}_{\rm off}$) compared to NMOFSETs. However, this study controls the leakage current of the GeSn NMOFSET device through adjustments in Ge fraction and in-volume biaxial strain. The channel length of the GeSn NMOSFET is 800 nm, with Si and in-volume biaxial strained Ge${}_{1-x}$Sn$_{x}$ serving as the substrate and channel, respectively. Device simulations were conducted on 81 device structures under various conditions to ensure comprehensive analysis through a material-and-device cooperative design. Fig. 6 shows the transfer curves of Ge${}_{1-x}$Sn$_{x}$ NMOSFETs at various Sn fractions and under in-volume biaxial stress. With increasing Sn fraction and tensile stress, both $I_{\rm on}$ and ${I}_{\rm off}$ increased due to bandgap narrowing and enhanced carrier mobility. Compressive strain effectively reduced ${I}_{\rm off}$, demonstrating that an optimization can be achieved to balance ${I}_{\rm on}$ and ${I}_{\rm off}$. In the case of tensile strain, the ${I}_{\rm on}$/${I}_{\rm off}$ maintains a high value of about 10${}^{8}$, and with compressive strain, it reaches approximately 10${}^{10}$, demonstrating superior on/off characteristics. Notably, compressive strain is suitable for implementing low-power devices by effectively reducing ${I}_{\rm off}$ while maintaining an appropriate level of ${I}_{\rm on}$. However, increasing either tensile stress or Sn fraction led to a degradation in the subthreshold swing (S). Finally, Fig. 7 presents the high-frequency performance, including current gain and ${f}_{\rm T}$, as a function of compressive strain in Ge${}_{0.937}$Sn${}_{0.063}$. A compressive strain of 0.5% in Ge${}_{0.937}$Sn${}_{0.063}$ yielded an ${f}_{\rm T}$ of 120 GHz, significantly higher than the 21 GHz for MOSFETs with bulk Ge channels and the 25 GHz for 1.0% tensile-strained Ge${}_{0.937}$Sn${}_{0.063}$ channels.

Fig. 6. Transfer curves of Ge${}_{1-x}$Sn$_{x}$ NMOSFETs at various Sn fractions under in-volume biaxial strain.

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Fig. 7. High-frequency performance as a function of Sn fraction and compressive strain, specifically at a Sn fraction of 6.3%.

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IV. CONCLUSION

In this work, a systematic study of Ge${}_{1-x}$Sn$_{x}$ was conducted using a bottom-up approach, linking material parameters and device design for greater credibility. The wide-range bandgap energy tunability and the indirect-to-direct bandgap transition of Ge${}_{1-x}$Sn$_{x}$ highlight its potential to address the current limitations of CMOS technology. Incorporating Ge${}_{1-x}$Sn$_{x}$ into the channel enhanced high-speed performance and suppressed off-state leakage, given an appropriate Sn fraction and stress, as concluded through material-device co-design.

ACKNOWLEDGMENTS

This work was supported by the research projects of the National Research Foundation of Korea (NRF) funded by the Korean Ministry of Science and ICT (MSIT) under grants 2021M3H4A6A01048300 and RS-2023-00258527.

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Soomin Kim
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Soomin Kim received the B.S. degree in electronic and electrical engineering from Ewha Womans University, Seoul, Korea, in 2023. She is currently pursuing an M.S. degree at Ewha Womans University. Her current research interests include novel semiconductor logic and memory devices in the nanoscale region, low-power synaptic devices and circuits, and scalable solid-state power source for CMOS integration. She is a Student Member of the Institute of Electronics and Information Engineeres (IEIE).

Hasan Ansari
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Hasan Ansari received the M.Tech. degree in nanotechnology from the Vellore Institute of Technology (VIT), Vellore, India, in 2016, and a Ph.D. degree in electrical engineering from the Indian Institute of Technology (IIT), Indore, India, in 2019. After his Ph.D., he worked as a Postdoctoral Fellow at Gachon University, South Korea, from 2019 to 2021. Currently, he is working as a Postdoctoral Research Fellow in the Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division at King Abdullah University of Science and Technology (KAUST). He is mainly interested in advanced logic, charge-trapping memory, emerging non-volatile memories, neuromorphic circuits, and in-memory and in-sensor computing.

Seongjae Cho
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Seongjae Cho received his B.S. and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 2004 and 2010, respectively. He worked as an Exchange Researcher at the National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan, in 2009. He worked as a Postdoctoral Researcher at Seoul National University in 2010 and at Stanford University, Palo Alto, CA, from 2010 to 2013. Also, he worked as a faculty member at the Department of Electronic Engineering, Gachon University, from 2013 to 2023. He is currently working as an Associate Professor at the Division of Convergence Electronic and Semiconductor Engineering, Ewha Womans University, Seoul, Korea from 2023. His current interests include emerging memory deviecs, advanced nanoscale CMOS devices, optical interconnect devices, and novel devices for future computing. He is a Life Member of IEIE.