I. INTRODUCTION

In recent years, the demand for artificial intelligence (AI) has increased owing to its widespread application and the expansion of its scope in various fields. Simultaneously, there is a growing need for advanced computing architectures with processing parallelism to process vast amounts of data effectively and make rapid decisions in complex situations. To address these challenges, neural computing inspired by the human brain has attracted considerable attention ^[1]. This approach uses highly interconnected synthetic neurons and synapses to model complex neural processes and solve difficult machine-learning problems ^[2]. By mimicking the distributed topology of the brain, neural systems provide significant advantages in terms of speed and energy efficiency, making them suitable for sophisticated information processing tasks ^[3,4]. In this approach, spiking neural networks (SNNs) have the potential to replicate the parallel processing capabilities and energy efficiency of the biological nervous system by mimicking the way neurons transmit information through electrical synapses in the form of spikes ^[5,6,7]. At the core of the SNN and neuromorphic architecture is the integrate-and-fire (I&F) neuronal circuit, which serves as a basic unit of computation that closely mimics the behavior of biological neurons ^[8,9,10,11]. In recent years, the digital implementation of I&F neuron models has attracted considerable attention as a promising alternative to analog models, providing flexibility, scalability, and smooth integration with conventional CMOS technologies ^{[12,13,14,15]}. These digital I&F models play an important role in building complex neural architectures, and serve as essential components of SNNs that can perform a wide range of cognitive tasks, such as recognition, classification, and decision-making ^[16,17].

Thus, in this study, we explore the implications of implementing digital I&F neuron models in neuromorphic computing systems. By utilizing the inherent parallelism and low-power characteristics of spiking neurons, these systems demonstrate considerable potential for the efficient and scalable implementation of AI algorithms ^[12,18]. Despite these developments, studies have continuously explored the future direction and prospects of digital I&F neuron models in the SNN domain. The continued development of digital circuit design combined with neuroscientific insights is expected to lead to the development of more sophisticated and energy-efficient neuromorphic systems, ultimately narrowing the gap between AI and biological intelligence ^[1,19,20]. This study explores the intersections of digital I&F neuron models, and evaluates their underlying principles. In addition, we investigate the ability of these models to accurately capture the spiking dynamics of biological neurons using field-programmable gate array (FPGA)-based programming and implementation efforts.

II. DESIGN OF DIGITAL NEURON MODEL

A. Digital integrate-and-fire neuron model

The I&F neuron model is a fundamental element of the SNN. This model integrates incoming signals and triggers an output spike when the membrane potential ($V_{\rm mem}$) reaches a specific threshold. After the spike is generated, it is transmitted to the connected neurons, resetting $V_{\rm mem}$ and preparing the neuron for the next cycle of integration and firing. In the digital implementation of the I&F neuron model, the analog behavior of biological neurons is replicated using digital circuits. The core components of the digital I&F neuron model include an integrator that accumulates input signals, a threshold comparator that determines when the accumulated potential exceeds a predefined voltage ($V_{\rm th}$), and a reset mechanism that restores $V_{\rm mem}$ to its initial state after spike generation.

Fig. 1 shows the logical flowchart used to achieve the digital equivalent circuit of an I&F neuron. The integrator unit accumulates the incoming spike signals (spike_in) over time, each of which is weighted by its synaptic weight. As these signals are integrated, $V_{\rm mem}$ increases until it surpasses the preset $V_{\rm th}$. When this threshold is exceeded, the comparator triggers an output spike (spike_out). Immediately after the spike is generated, the membrane potential is reset to 0 V, allowing the neurons to begin a new integration process. This cycle of integration, threshold comparison, and spike generation verifies the essential behaviors of an I&F neuron circuit. This digital implementation provides accurate control over neuronal parameters, such as time constants and critical voltages, and can be tailored to specific applications. Owing to the flexibility and adaptability of the digital I&F neuron circuit, it is suitable for a wide range of neural computing tasks ranging from basic pattern recognition to complex cognitive functions. This compact design also enables efficient expansion, making it easier to achieve a large-scale SNN in the neural system.

Fig. 1. Workflow of the digital equivalent I&F neuron model.

B. FPGA implementation of an I&F neuron

The I&F neuron model was implemented in a Zynq multiprocessor system-on-chip (MPSoC) FPGA using the Xilinx Vivado Design Suite. First, a hardware description language (HDL) representation of the I&F neuron model was developed. This HDL code defines neuron behavior, including signal integration, threshold detection, spike generation, and membrane potential resetting. Then, an analog-to-digital converter module was used to digitize the continuous input current fed into the analog I&F neuron. This allowed the HDL-based design methodology to build an I&F neuron circuit by replacing analog components by equivalent digital ones.

In the simulation, a reset signal was first enabled to create the initial conditions. After a short delay of $1\times$ unit, the reset signal was toggled, starting with the main simulation sequence. The program algorithm proceeded in a loop simulation clock cycle. The input spike signal was enabled and toggled after each $1\times$ unit interval. The integral $V_{\rm mem}$ was monitored. If it exceeded a given $V_{\rm th}$, the comparator triggered the generation of an output spike (spike_out). $V_{\rm mem}$ was then reset to 0 V, allowing the neurons to resume the integration process. Subsequently, we simulated a neuron reset event by enabling the neuron_reset signal for $1\times$ unit of the clock signal. This sequence was repeated until the clock signal stopped, as shown in Fig. 2. The simulation results validate the functionality of the digital I&F neuron circuit, and provide important insights into its dynamic behaviors. These results demonstrate the ability of this circuit to accurately replicate the spiking dynamics of biological neurons, making it a suitable candidate for the hardware-oriented nervous system. The FPGA implementation is optimized to minimize resource usage, allowing the digital I&F neuron circuit to be scaled to accommodate larger neuronal networks.

Fig. 2. Simulation of the designed digital equivalent of an I&F neuron using the Vivado Design Suite.

III. RESULTS AND DISCUSSION

The FPGA implementation of the digital I&F neuron model was thoroughly analyzed to evaluate its performance in terms of resource utilization, power consumption, and overall design efficiency. These results provide a deeper understanding of the behaviors of neurons and enhance the reliability, cost-effectiveness, and compactness of the model. Table 1 provides an overview of the FPGA resources used to implement the I&F neuron digital circuit. The design utilizes only a minimal portion of the available resources, ensuring a simple and efficient implementation. Specifically, only 11 of the 274,080 lookup tables (LUTs) were used, representing a utilization rate of only 0.01%. Similarly, only 33 flip-flops (FFs) were required out of the 548,160 available units, corresponding to a utilization rate of 0.01%. Of the 328 pins provided by the FPGA system for input/output (IO), only five (1.52%) were sufficient to implement the neuron circuit. In addition, only one clock buffer (BUFG) was used out of the 404 available units, representing only 0.25% of the total. These results indicate that the design is highly resource-efficient, with ample room for further optimization and enhancement. As shown in Fig. 3, the total on-chip power consumption was measured to be 0.71 W, with the junction temperature maintained at 25.7 $^\circ$C. The power consumption is clearly lower than the values obtained from the comparable FPGAs in the recent reports, 4.5 W, 4.6 W, and 10.5 W ^[21,22,23]. These metrics highlight the efficiency of the design, and suggest that the digital I&F neuron circuit, successfully implemented and verified on the Zynq MPSoC FPGA, is well suited for integration into fully CMOS-based SNN chips. Also, although the number of components making up the FPGA and the usage portions can differ, the implementation design in this work can be adopted to other FPGA platforms with minor adjustments such as clocking and resource optimization due to its modular structure.

Fig. 3. Power consumption per function in the digital equivalent I&F neuron circuit for an SNN realized using an FPGA.

The successful implementation and validation of this digital neuron circuit underscore its potential as a platform for neuromorphic computing applications. Its compact design, combined with low power consumption and minimal resource utilization, makes it a promising candidate for scaling into larger and more complex SNNs. Although there have been substantial challenges in optimizing the bit widths, reusing the computational units, and balancing efficiency and precision, trade-off relation has been precisely controlled to obtain permissible precision and scalability, achieving resource and power efficiencies. Replacing analog components introduces quantization and discretization effects due to finite bit widths, slightly impacting precision. However, optimal bit-width selection ensures functional accuracy and repeatability, which is advantageous for large-scale systems. This study not only confirms the functionality of the I&F neuron model, but also demonstrates its feasibility for future neuromorphic systems that require efficient and scalable hardware solutions.

IV. CONCLUSION

In this study, we successfully designed, implemented, and verified the digital equivalent circuit of an I&F neuron model using the FPGA technology. The functionality and performance of the neuron circuit were validated, demonstrating that it is effective in replicating biological neuron behaviors. Furthermore, the compact design and detailed power analysis of individual functional blocks highlight the efficiency of the proposed circuit and its strong potential for integration into hardware-oriented neural systems. A quantitative evaluation of component usage and power consumption further confirms the viability of the proposed circuit for scalable and energy-efficient applications in advanced neural computing and its chip implementation.