Mobile QR Code QR CODE

The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

Journal Search

  1. Home
  2. Archive
  3. 2025-04 (Vol.25 No.02)
  4. 10.5573/JSTS.2025.25.2.123
XML PDF INFO REF

References

1 
C. Mead, ``Neuromorphic electronic systems,'' Proceedongs of IEEE, vol. 78, no. 10, pp. 1629-1636, Oct. 1990.DOI
2 
C. D. Schuman, T. E. Potok, R. M. Patton, J. D. Birdwell, M. E. Dean, G. S. Rose, and J. S. Plank, ``A survey of neuromorphic computing and neural networks in hardware,'' arXiv:1705.06963, 2017.DOI
3 
S. Furber, ``Large-scale neuromorphic computing systems,'' Journal of Neural Engineering, vol. 13, no. 5, pp. 051001-1--051001-14, Aug. 2016.DOI
4 
D. Markovic, A. Mizrahi, D. Querlioz, and J. Grollier, ´ “Physics for neuromorphic computing,” Nature Reviews Physics, vol. 2, pp. 499-510, Jul. 2020.DOI
5 
Q. T. Pham, ``A review of SNN implementation on FPGA,'' Proc. of 2021 International Conference on Multimedia Analysis and Pattern Recognition (MAPR), pp. 1-6, Hanoi, Vietnam, Oct. 15-16, 2021.DOI
6 
W. Maass, ``Networks of spiking neurons: The third generation of neural network models,'' Neural Networks, vol. 10, no. 9, pp. 1659-1671, Aug. 1997.DOI
7 
J.-Q. Yang, R. Wang, Y. Ren, J. Y. Mao, Z.-P. Wang, Y. Zhou, and S.-T. Han, ``Neuromorphic engineering: From biological to spike-based hardware nervous systems,'' Advanced Materials, vol. 32, no. 52, pp. 2003610-1--2003610-32, Dec. 2020.DOI
8 
S. Yang, P. Liu, J. Xue, R. Sun, and R. Ying, ``An efficient FPGA implementation of Izhikevich neuron model,'' Proc. if 2020 International SoC Design Conference (ISOCC), pp. 141-142, Yeosu, Korea, Oct. 21-24, 2020.DOI
9 
J. Han, Z. Li, W. Zheng, and Y. Zhang, ``Hardware implementation of spiking neural networks on FPGA,'' Tsinghua Science and Technology, vol. 25, no. 4, pp. 479-486, Jan. 2020.DOI
10 
S. Schmidgall, R. Ziaei, J. Achterberg, L Kirsch, S. P. Hajiseyedrazi, and J. Eshraghian, ``Brain-inspired learning in artificial neural networks: A review,'' APL Machine Learning, vol. 2, no. 2, pp. 021501-1--021501-14, Jun. 2024.DOI
11 
A. N. Burkitt, ``A review of the integrate-and-fire neuron model: I. Homogeneous synaptic input,'' Biological Cybernetics, vol. 95, no. 1, pp. 1-19, Apr. 2006.DOI
12 
M. Kwon, M. Baek, S. Hwang, K. Park, T. Jang, T. Kim, J. Lee, S. Cho, and B.-G. Park, ``Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation,'' Journal of Applied Physics, vol. 124, no. 15, pp. 152107-1--152107-7, Sep. 2018.DOI
13 
G. Indiveri, E. Chicca, and R. Douglas, ``A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity,'' IEEE Transactions on Neural Networks, vol. 17, no. 1, pp. 211-221, Jan. 2006.DOI
14 
J. Schemmel, D. Brüderle, A. Grübl, M. Hock, K. Meier, and S. Millner, “A wafer-scale neuromorphic hardware sys- tem for large-scale neural modeling,” Proc. of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1947-1950, Paris, France, May 30-Jun. 2, 2010.DOI
15 
J. Seo, B. Brezzo, Y. Liu, B. D. Parker, S. K. Esser, and R. K. Montoye, ``A 45 nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons,'' Proc. of IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, San Jose, USA, Sep. 19-21, 2011.DOI
16 
M. Pfeiffer and T. Pfeil, ``Deep learning with spiking neurons: Opportunities and challenges,'' Frontiers in Neuroscience, vol. 12, pp. 774-1--774-18, Oct. 2018.DOI
17 
H. Taherdoost, ``Deep Learning and Neural Networks: Decision-Making Implications,'' Symmetry, vol. 15, no. 9, pp. 1723-1--1723-22, Sep. 2023.DOI
18 
P. Panda, S. A. Aketi, and K. Roy, ``Toward scalable, efficient, and accurate deep spiking neural networks with backward residual connections, stochastic softmax, and hybridization,'' Frontiers in Neuroscience, vol. 14, pp. 653-1--653-18, Jun. 2020.DOI
19 
G. Indiveri and T. K. Horiuchi, ``Frontiers in Neuromorphic Engineering,'' Frontiers in Neuroscience, vol. 5, pp. 118-1--118-2, Oct. 2011.DOI
20 
G. Indiveri, B. Linares-Barranco, R. Legenstein, G. Deligeorgis, and T. Prodromakis, ``Integration of nanoscale memristor synapses in neuromorphic computing architectures,'' Nanotechnology, vol. 24, no. 38, pp. 384010-1--384010-13, Sep. 2013.DOI
21 
H. Fang, Z. Mei, A. Shrestha, Z. Zhao, Y. Li, and Q. Qiu, ``Encoding, model, and architecture: Systematic optimization for spiking neural network in FPGAs,'' Proc. of 2020 IEEE ACM International Conference on Computer-Aided Design (ICCAD), pp. 1-9, Virtual, Nov. 2-5, 2020.DOI
22 
X. Ju, B. Fang, R. Yan, X. Xu, and H. Tang, ``An FPGA implementation of deep spiking neural networks for low-power and fast classification,'' Neural Computation, vol. 32, no. 1, pp. 182-204, Jan. 2020.DOI
23 
S. Yang, J. Wang, B. Deng, C. Liu, H. Li, C. Fietkiewicz, and K. A. Loparo, ``Real-time neuromorphic system for large-scale conductance-based spiking neural networks,'' IEEE Transactions on Cybernetics, vol. 49, no. 7, pp. 2490-2503, Apr. 2018.DOI