KimGyu-Beom1
NamChan-Hyeok1
KimYeon Seok1
ParkJoon Hyeong3
KwonJiseok2*
BaekMyung-Hyun1*
-
(Department of Electronic and Semiconductor Engineering, Gangneung- Wonju National
University, Gangneung, 25457, Republic of Korea)
-
(School of Information, Communications and Electronic Engineering, The Catholic University
of Korea, Bucheon, 14662, Republic of Korea 3 Birck Nanotechnology Center, Purdue
University, West Lafayette, Indi- ana 47907, USA)
-
(Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907, USA)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
DRAM, pass gate effect (PGE), gate-induced drain leakage (GIDL), vertical DRAM
I. INTRODUCTION
The rapid advancement of Artificial Intelligence (AI) and the Fourth Industrial Revolution
has significantly increased the demand for higher data processing speeds and enhanced
computational power. Dynamic Random-Access Memory (DRAM), as the primary memory in
von Neumann architecture, is now under pressure to deliver greater integration density
and performance. However, as DRAM cell transistor dimensions scale down to the sub-40
nm regime, issues such as the Short Channel Effect (SCE) become more prominent. To
address these challenges, various innovative technologies have been explored to refine
DRAM cell design, with the aim of preserving performance and reliability. The Buried
Channel Array Transistor (BCAT) structure was a significant innovation described in
[1], designed to mitigate SCE by increasing the effective channel length through a buried
gate structure. Despite these advancements, DRAM technology faces substantial challenges
as cell design rules shrink below 10 nm. In response to these limitations, Samsung
Electronics introduced a novel architecture known as the S2CAT structure in December
2023 [2]. The S2CAT architecture vertically integrates DRAM cell transistors, offering a promising
solution to the limitations faced by conventional BCAT.
In 3D vertical DRAM structures, electrical interference arises from neighboring cells,
leading to reliability issues such as Pass Gate Effect (PGE) and Row Hammer. In this
paper, we investigate the principle of PGE in 3D vertical DRAM and its effects. PGE
is a phenomenon in which the threshold voltage (V${}_{\rm t}$) decreases as a result
of the activation of a neighboring cell. This phenomenon affects the hold behavior
of DRAM, leading to issues such as increased leakage current, which can ultimately
result in read failures.
In addition, vertical DRAM employs a floating body structure [2]. When Gate-Induced Drain Leakage (GIDL) occurs, the generated holes cannot sink through
the body contact, lowering the channel's energy band. This lowers electron tunneling
from the valence to the conduction band at the drain, ultimately reducing the severity
of GIDL [3]. However, this can also exacerbate channel off-leakage due to the lower energy band,
further degrading DRAM performance.
In this study, we implemented a vertical DRAM device using 2D Technology Computer-Aided
Design (TCAD) simulations to investigate additional problems caused by PGE, as well
as GIDL resulting from structural changes [4].
II. PASS GATE EFFECT
PGE is one of the disturbance characteristics of DRAM and is a significant issue affecting
the stability and performance of DRAM cells. DRAM has a cell array structure in which
a large number of cells are integrated, each consisting of one access transistor and
one storage capacitor to store data. As technology advances, the size of the cells
decreases, increasing inter-cell interference between them. One such inter-cell interference
is PGE, as discussed in [5,6]. This refers to a phenomenon where adjacent cells are unintentionally affected when
the gate of a particular cell operates. In this context, the cell that is unintentionally
influenced by the operation of an adjacent cell is referred to as the `victim cell,'
while the cell whose gate operation induces this unintended effect is called the `aggressor
cell.' When the gate of the aggressor cell is turned on, the source-to-channel energy
barrier of the adjacent victim cell decreases, resulting in a reduction of V${}_{\rm
t}$. PGE is a critical factor in DRAM design, particularly in high-density memory
applications [7,8,9,10,11]. This is because, as DRAM design becomes smaller and the spacing between cells is
reduced, PGE-induced interference becomes more pronounced. Therefore, DRAM designers
must carefully plan the physical dimensions of cells and voltage conditions to minimize
this PGE effect.
Table 1. Parameters of the vertical DRAM structure.
Table 2. Voltage conditions for each phenomenon in vertical DRAM.
III. SIMULATION CONDITION
In this study, a vertical DRAM structure was simulated using Silvaco TCAD. The structure
used in the simulation was designed to be similar to that of S2CAT, as shown in Fig. 1. In Fig. 1, Word Line 1 (WL1) indicates the gate node of victim cell. Word Line 2 (WL2) depicts
the gate node of aggressor cell. Through Storage Node Contact (SNC), select transistor
is connected to the storage capacitor. The opposite side of SNC will be connected
to Bit Line (BL). The Back Gate (BG) is located between adjacent cells. The main dimensions
applied in the simulation are summarized in Table 1, including an effective channel
length of 50 nm, a BG thickness of 20 nm, and an oxide thickness of 5 nm. The device
modeling was carried out using the Shockley-Read-Hall model, the Lombardi Mobility
Model, band-to-band tunneling, and Selberherr's Model.
The bias conditions for the simulation are shown in Table 2. In particular, the victim
cell had a voltage of 0 V applied to its gate to maintain a stable hold state and
create an off state. When 3 V was applied to the gate of the aggressor cell, PGE occurred,
which reduced the source-to-channel energy barrier of the victim cell and lowered
its threshold voltage. These voltage conditions reflect those that may occur in actual
DRAM operating environments. Additionally, to observe the GIDL phenomenon in vertical
DRAM, the following voltage conditions were applied: -0.5 V to the gate of a WL1 and
1.5 V to the SNC, while the WL2 was grounded.
Fig. 1. Schematic diagram for vertical DRAM.
IV. EXPERIMENTAL RESULTS
1. Pass Gate Effect
To assess the utility of the BG, an initial simulation was performed using a structure
where the BG region was replaced with an oxide layer. The inset in Fig. 2. illustrated the structure of a vertical DRAM cell without a BG, where the BG is
replaced by an oxide layer between the cells. The graph in Fig. 2. shows the transfer characteristics of the victim cell. This confirms the variation
in the V${}_{\rm t}$ of the victim cell as the WL2 voltage is adjusted from -1 to
3 V. When a positive voltage is applied to the WL2, the V${}_{\rm t}$ of the victim
cell is reduced. This phenomenon can be explained by the energy band shift caused
by the voltage difference, as shown in Fig. 3. The energy band shift is observed by cutting along a line parallel to the channel
of the victim cell. When a positive voltage 3 V is applied, the peak energy level
of the conduction band decreases by 0.04 eV compared to the state with 0 V applied.
The transfer characteristics of the victim cell in the vertical DRAM, using air as
a low-k material, is shown in Fig. 4. The voltage was applied following the same procedure as in earlier cases, allowing
for the observation of threshold voltage variations. Due to the lower dielectric constant
of air compared to an oxide-filled structure, the electric field by the WL2 is reduced.
As depicted in Fig.~5, when the aggressor cell voltage is set to 0 V and 3 V, respectively,
the peak conduction band energy shows a difference of 0.01 eV.
Fig. 6(a) presents an equivalent circuit model that represents an ideal capacitor connected
in series, developed based on the findings of prior experiments. This circuit consists
of two-word lines, WL1 and WL2.
WL1 is grounded, while a voltage of 3 V is applied to WL2. The corresponding equivalent
capacitances, labeled as C${}_{eq1}$ and C${}_{eq2}$, are connected in series. The
dielectric constants of the air and oxide layers differ, and the capacitance of each
layer is determined by its respective dielectric constant and thickness. The potential
values at the points indicated by the arrows in Fig. 6(a) were calculated using the equation provided in Fig. 6(b). Table 3 provides a quantitative analysis of the effect of air thickness on potential
values, offering a detailed assessment of this relationship. Fig. 6(c) compares theoretical calculations with simulated data, illustrating the relationship
between potential and air thickness. Both curves exhibit a decreasing trend as the
air thickness increases, emphasizing the influence of this parameter on the potential
behavior. When the air thickness is 0 nm, measurements were conducted using only the
oxide layer without the air component. The difference between theoretical and simulated
values is primarily due to parasitic capacitance and electric field effects within
the actual device, which are not fully accounted for in the theoretical model. These
findings validate the reliability of the PGE data obtained in previous experiments.
Mathematical calculations were performed to verify the validity of the experimental
approach, and the consistency between simulation results and theoretical trends supports
the accuracy and robustness of the methodology used.
Fig. 2. Transfer characteristics of the victim cell without a BG structure. Various
WL2 bias conditions were applied to analyze the PGE. Inset: Schematic diagram of the
simulated structure.
Fig. 3. Energy band diagram of the WL1. The difference in peak energy between the
two conditions is 0.04 eV.
Fig. 4. Transfer characteristics of WL1 in a structure replaced with air as a low-dielectric
material.
Fig. 5. Energy band diagram for the structure with air gap. The difference in the
energy band between the two voltage conditions has been reduced.
Fig. 6. Equivalent circuit model of series-connected capacitors. (b) Formula for calculating
the voltage at WL1 in the circuit. (c) Quantitative analysis of the effect of air
thickness on voltage.
Table 3. Comparison of theoretical and simulation voltage values.
Fig. 7 illustrates the transfer characteristics of the victim cell in vertical DRAM with
an applied BG. The BG voltage was maintained at 0 V, ensuring that the threshold voltage
of the victim cell was unaffected by the activation of the aggressor cell. This demonstrates
that the BG effectively shields the electric field generated by the WL2 bias. As shown
in Fig. 8, when the aggressor cell voltage is varied between 0 V and 3 V for comparison, no
change is observed in the energy band profile. These findings confirm that incorporating
the BG effectively suppresses the PGE [12,13,14,15].
Fig. 9 shows the I${}_{d}$-V${}_{g}$ curve when the BG voltage is applied at 0.5 V intervals
from -1 V to 1 V. In vertical DRAM, various voltages are applied to the BG, resulting
in changes to the V${}_{\rm t}$. This process is referred to as BG modulation. A negative
BG voltage increases the V${}_{\rm t}$, while a positive BG voltage decreases it.
These changes in V${}_{\rm t}$ affect DRAM performance, particularly access speed
and power consumption. TCAD simulations demonstrate that applying a negative voltage
to the BG effectively suppresses leakage current.
Fig. 10. illustrates the variation in off-state leakage current across different WL2 voltages.
The gate voltage of the victim cell was varied from -2 V to 3 V, while the SNC voltage
was held constant at 1 V. To assess the effect of the BG, the gate voltage of the
WL2 was also varied within the same range of -2 V to 3 V. The off-state leakage current
was measured at the point where the WL1 voltage was fixed at -0.25 V. When the BG
was replaced with an oxide layer, the leakage current increased as a positive voltage
was applied to WL2, indicating the occurrence of potential interference. In contrast,
the incorporation of the BG effectively suppressed this interference.
Fig. 7. Transfer characteristics of victim cells with BG, showing no change in behavior
despite varying WL2 voltage.
Fig. 8. nergy band diagram of the structure with a BG. The energy bands remain consistent
across varying WL2 voltages.
Fig. 9. Transfer characteristics by varying BG bias.
Fig. 10. Variation of off current with and without BG when various WL2 voltage was
applied.
2. Gate Induced Drain Leakage
In DRAM hold operation, the cell transistor experiences a GIDL condition, leading
to the formation of electron-hole pairs [11]. In conventional DRAM, the generated electrons contribute to leakage for data '1,'
while the generated holes escape through the body contact. However, in vertical DRAM
structures, the absence of a body contact introduces additional issues. As shown in
Fig. 11, this phenomenon occurs when the generated holes cannot sink-out via the body contact
terminal, leading to their accumulation within the silicon channel. This results in
observable transient characteristics during the hold operation.
Fig. 12. shows the variation in hole concentration over retention time (hold time) during
the occurrence of GIDL in vertical DRAM. The inset of Fig. 12. includes the vertical DRAM structure, with a cutline drawn in the specified direction
to analyze the channel hole concentration. The simulation was performed under conditions
where a voltage of -0.5 V was applied to the WL1 and 1.5 V to the SNC to investigate
the GIDL phenomenon and its effect on electron-hole pair generation. The results show
that the hole concentration increases by more than 100 times when comparing retention
times of 1 ms and 10 s.
Fig. 13. illustrates a transient simulation of off-state leakage current that replicates
the hold-state operation in an actual DRAM. Over time, the source-to-channel energy
barrier gradually decreases due to the accumulation of holes. Initially, this accumulation
reduces the total leakage current caused by the GIDL effect. However, as the energy
barrier continues to decrease, channel off-leakage is promoted, leading to an overall
increase in the total leakage current.
Fig. 11. GIDL condition and charge accumulation in vertical DRAM during hold operation.
Fig. 12. Hole concentration profile in vertical DRAM under GIDL condition. As the
retention time increases, the number of holes accumulated in silicon increases.
Fig. 13. Transient variation of drain current due to GIDL reduction and channel off-leakage
increase.
V. CONCLUSIONS
In this study, an experiment was conducted to investigate the interference between
adjacent cells in the vertical DRAM structure with and without a BG. A structure with
BG was used as the control group, while in the experimental group, materials were
varied based on their dielectric constants, which determine capacitance, to examine
the effect on the PGE. Results confirmed that PGE decreases as the dielectric constant
decreases. Theoretical trends matched simulation results, validated by capacitance
equivalent circuit calculations. Moreover, analysis of the victim cell's V${}_{\rm
t}$ variation led to the conclusion that PGE is not effectively prevented in the absence
of BG. However, in the structure with BG, PGE was reduced by 99.94% due to the shielding
effect. TCAD simulations further showed that during GIDL in the floating body structure,
holes accumulate over time, which leads to an increase in leakage current by lowering
the source-to-channel energy barrier. Therefore, the results of this study contribute
to advancements in DRAM technology and suggest future applications.
ACKNOWLEDGMENTS
This research was supported by Semiconductor R&D Support Project through the Gangwon
Technopark (GWTP) funded by Gangwon Province (No. GWTP 2024-029). This paper was also
supported by research funds for newly appointed professors of Gangneung-Wonju National
University in 2023.
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Gyu-Beom Kim received his B.S. degree in electronic engineering from Gangneung-Wonju
National University, Gangneung, Korea, in 2024, and is currently pursuing an M.S.
degree. His research interests include next-generation memory semiconductor devices
and neuromorphic synaptic devices.
Chan-Hyeok Nam received his B.S. degree in electronic engineering from Gangneung-Wonju
National University, Gangneung, Korea, in 2024, and is currently pursuing an M.S.
degree. His research interests include next-generation memory semiconductor and neuromorphic
synaptic devices.
Yeon Seok Kim has been studying in the Department of Electronic Engineering at
Gangneung-Wonju National University (GWNU, Korea) from 2019 to 2023, also he has now
been working on M.S. course at GWNU. His current research interests include MOS devices
for DRAM memory at the Nanoscale Semiconductor Research Laboratory (NSRL) according
to Professor Myung-Hyun Baek.
Joon Hyeong Park received his Ph.D. degree from the Department of Agricultural
and Biological Engineering at Purdue University (West Lafayette, IN, USA) in 2016.
In 2016, he joined Birck Nanotechnology Center as a research engineer. His research
focuses on lithography process, atomic force microscopy, and 2D material.
Jiseok Kwon received his Ph.D. degree from the Department of Electrical and Computer
Engineering at Purdue University (West Lafayette, IN, USA) in 2019. After Ph. D.,
he worked at Samsung semiconductor R & D center as a staff engineer from 2020 to 2023.
In 2023, he joined The Catholic University of Korea (CUK, Korea) as an assistant professor
in the school of Information, Communications and Electronic Engineering. His research
focuses on the experimental characterization of novel nano materials and fabrication
of high performance, low power electronic devices. He also works on device and circuit
modeling and optimization of novel nano transistors for RF applications.
Myung-Hyun Baek received his B.S degree in electrical engineering from Seoul National
University (SNU), Seoul, Korea, in 2013, and his Ph.D. degree in Electrical and Computer
Engineering from SNU, Seoul, Korea, in 2020. He worked at Samsung Electronics Co.,
Ltd. (Hwasung, Korea) as a Staff Engineer from 2020 to 2023. In 2023, he joined Gangneung-Wonju
National University (GWNU, Korea) as an assistant professor in the Department of Electronics
and Semiconductor Engineering. His main research interests are nonvolatile memory
technologies and neuromorphic systems.