1. Operation of Conventional Dynamic Comparators

Fig. 3(a) shows the conventional decision circuitry of the PAM-4 receiver. The decision circuitry consists of 3 dynamic comparators. If V${}_{\rm INP}$ is greater than V${}_{\rm INN}$, the LSB is determined by the output of one `determinative dynamic comparator' (dashed line block in Fig. 3(a)). Figs. 3(b) and 3(c) show the dynamic comparators of Strong-ARM latch comparator ^[5,6] and double-tail comparator ^[7,8], respectively. Their operations are shown in Fig. 4. The operations of the two conventional dynamic comparators are similar and described in three phases ^[6,8]. 1) When the clock (CLK) is low, the dynamic comparator is in the reset phase. In the case of StrongARM comparator, the two outputs $($V${}_{\rm OUTP}$, V${}_{\rm OUTN})$ are pre-charged with supply voltage (VDD), and in the case of double-tail comparator, they are reset to ground voltage (GND). In both cases, V${}_{\rm CP}$ and V${}_{\rm CN}$ are pre-charged with VDD. 2) When the clock rises, the dynamic comparator reaches the sampling phase. At this time, V${}_{\rm CP}$ and V${}_{\rm CN}$ fall to GND, and their falling rates are differentiated by ${\rm V}_{\rm INP} -{\rm V}_{\rm INN} -{\rm V}_{\rm LSB,TH}$. The V${}_{\rm OUTP}$ and V${}_{\rm OUTN}$ fall or rise at different rates, and the sign of their difference $({\rm V}_{\rm OUTP}-{\rm V}_{\rm OUTN})$ is determined by that of ${\rm V}_{\rm CP} - {\rm V}_{\rm CN}$. 3) When the clock stays high, the dynamic comparator reaches the regeneration phase, then V${}_{\rm OUTP}$ and V${}_{\rm OUTN}$ go to the rail-to-rail level.

Fig. 3. (a) Block diagram of conventional decision circuitry with comparators in PAM-4 receiver. (b) Conventional Strong-ARM latch comparator. (c) Conventional double-tail comparator.

Fig. 4. Operation of conventional dynamic comparators.

2. Effective LSB Threshold Voltage of Conventional Dynamic Comparators

Fig. 5 shows a circuit model of a conventional dynamic comparator in the sampling phase after the clock rises. Let V${}_{\rm IN,CM}$ and V$_{\rm IN,DM}$ be the common-mode level and difference of the input voltages, respectively, and then let V${}_{\rm TH,CM}$ and V${}_{\rm TH,DM}$ be those of the reference voltages. If V${}_{\rm IN,DM}$ equals V${}_{\rm LSB,TH}$, then I${}_{\rm OP}$ and I${}_{\rm ON}$ will be the same, and also the falling rates of V${}_{\rm CP}$ and V${}_{\rm CN}$. Therefore, the cross-coupled pair is in a metastable state, and the data is determined to be 0 or 1 with a 50% probability for each. Let's call this state a `threshold-boundary condition'. From the relation of ${\rm I}_{\rm OP} ={\rm I}_{ON}$, we obtain the following where V${}_{\rm T}$ is the threshold voltage of M${}_{1\sim 4}$.

If V${}_{\rm IN,CM}$ is large enough, the V${}_{\rm LSB,TH}$ will be inversely proportional to V${}_{\rm IN,CM}$ as follows:

Otherwise, if V${}_{\rm IN,CM}$ is small enough, the V${}_{\rm LSB,TH}$ looks diverging. For such a threshold boundary condition, V${}_{\rm INP}$ and V${}_{\rm INN}$ are very high or very low. Therefore, we must consider the `velocity saturation' ^[9,10] of M${}_{1}$ and the fact that minimal current flows in M${}_{4}$. Velocity saturation is noticeable when the overdrive voltage is substantial. Then the gate voltage-drain current relation remains no longer a quadratic function but approaches a first-order function where v${}_{\rm sat}$ is the saturation velocity of M${}_{1}$.

Taking this into account, the expression for the current at the threshold boundary condition can be rewritten as follows:

To summarize, if V${}_{\rm IN,CM}$ is small enough, the V${}_{\rm LSB,TH}$ is modeled as a first-order function with a slope of ($-2$) with respect to V${}_{\rm IN,CM}$. Meanwhile, depending on the relative size of M${}_{\rm TAIL}$, the average value of V${}_{\rm TAIL}$ is variable. To account for this, the V${}_{\rm LSB,TH}$ can be expressed as follows:

Thus, it can be seen that the conventional structures have a linear V${}_{\rm LSB,TH}$ variation as the V${}_{\rm IN,CM}$ varies. Section V.1 will compare the above quantitative expression with simulation result.

Fig. 5. Circuit model of the conventional dynamic comparator on sampling phase.

1. Circuit Description

The block diagram of the proposed structure is shown in Fig. 6, where M${}_{1\sim 8}$, M${}_{\rm TAIL1,TAIL2}$, and MDEGEN1,DEGEN2 represent linear pre-amplifiers, and M${}_{\rm R1\sim R8}$ are non-linear summers. This structure borrows the basic form of the double-tail comparator ^[7] and can be viewed as a single circuit stage for determining both MSB and LSB.

Fig. 6. Schematic of proposed referenceless dynamic comparator.

There are two linear pre-amplifiers : the left-side block making the difference between V${}_{\rm CP}$ and V${}_{\rm CN}$ proportional to the difference in the input voltages (${\rm V}_{\rm INP} -{\rm V}_{INN}$), and the right-side block making V${}_{\rm BB}$ independent to ${\rm V}_{\rm INP}-{\rm V}_{\rm INN}$.

The next stage consists of non-linear summers. The nonlinear summer output two currents proportional to the sum of the squares of the two over-drive voltages.

As the difference in the input voltages increases, the difference between V${}_{\rm CP}$ and V${}_{\rm CN}$ increases, and the I${}_{\rm C}$ increases accordingly. However, for V${}_{\rm BB}$, even if the difference in the input voltages increases, I${}_{\rm B}$ remains almost unchanged. Therefore, depending on the value of I${}_{\rm B}$ or the falling rate of V${}_{\rm BB}$, V${}_{\rm LSB,TH}$ is determined to be a specific value.

In the proposed dynamic comparator, the V${}_{\rm LSB,TH}$ is regulated by the threshold code (${\rm BIT}<4:0>$). Therefore, it does not require any analog reference voltages. As the threshold code increases, the V${}_{\rm BB}$'s falling rate increases, so the V${}_{\rm LSB,TH}$ decreases, as shown in Fig. 7.

Fig. 7. Simulated effective LSB threshold voltage as a function of the threshold bit code in case of ${\rm V}_{\rm IN,CM} = 600$ mV, 800 mV, and 1000 mV.

In the proposed structure, only one comparator is required to make one decision circuitry, whereas three comparators are required in double-tail comparator-based structure. The hardware and power consumption of the proposed decision circuitry can be expected to be 33% lower than that of the decision circuitry consisting of the double-tail comparators. In addition, the proposed structure does not require analog reference voltages and their generator, which can be expected to save more hardware and power in the receiver design.

2. Operation of Proposed Dynamic Comparator

Fig. 8 shows the operation of the proposed dynamic comparator. The operation of the proposed dynamic comparator can also be explained in three phases. 1) When the clock is low, all outputs are reset to GND by M${}_{3,4,7,8}$ and M${}_{\rm R1\sim R8}$. 2) After the clock rises, when a signal with ${\rm LSB} = 0$ (gray-code) is input in the sampling phase, ${\rm V}_{\rm CP} - {\rm V}_{\rm CN}$ is amplified large enough. At this time, the average value of I${}_{\rm C}$ becomes larger than that of I${}_{\rm B}$, then the LSB signal is pulled down and the LSBB opposite. For an incoming signal with ${\rm LSB} = 1$, vice-versa. 3) When the clock stays high, the comparator reaches the regeneration phase, then LSB and LSBB go to the rail-to-rail level. For the circuitry with MSB decision, the connections of the MOSFETs are the same as for the double-tail comparator ^[7] except for a dummy block with M${}_{\rm R5,R8}$ for load balance. Therefore, the proposed dynamic comparator has virtually the same operation with respect to MSB decision as a the 2-input double-tail comparator, as shown in the bottom graph of Fig. 8.

Fig. 8. Operation of proposed referenceless dynamic comparator.

3. Effective LSB Threshold Voltage of Proposed Dynamic Comparator

Fig. 9 models a proposed dynamic comparator in the sampling phase after the clock rises. The threshold boundary condition of the proposed structure can be analyzed by comparing the average values of the I${}_{\rm C}$ and I${}_{\rm B}$. The average values of I${}_{\rm C}$ and I${}_{\rm B}$ correspond to the amount of charge transferred to the cross-coupled pair through them, which can be calculated by integrating I${}_{\rm C}$ and I${}_{\rm B}$ over time. If we interpret each linear amplifier stage as a differential pair, then V${}_{\rm CP}$, V${}_{\rm CN}$, and V${}_{\rm BB}$ are

The expression for the threshold boundary condition can be expanded as follows:

All the currents I${}_{\rm R1, R2, R3, R4}$ have the same integral value because they have the same current-voltage relation, regardless of how the relation is modeled. But their coefficients are different. Then the threshold voltage can be expressed as follows:

V${}_{\rm LSB,TH}$ is defined by three parameters: g${}_{\rm m1,2}$, I${}_{\rm TAIL,1}$, and I${}_{\rm TAIL,2}$. If the linear pre-amplifiers were modeled as the ideal differential pairs, then the three parameters are independent of V${}_{\rm IN,CM}$. As a result, it can be expected that the proposed structure is insensitive to V${}_{\rm IN,CM}$ variation. More qualitatively, V${}_{\rm CP}$, V${}_{\rm CN}$, and V${}_{\rm BB}$ are independent of V${}_{\rm IN,CM}$ due to the common-mode-rejection capability of the differential amplifiers, which results in less variability in V${}_{\rm LSB,TH}$. As in Eq. (8), the above quantitative expression will be compared to simulation result in Section V.1.

Fig. 9. Circuit model of the proposed referenceless dynamic comparator on sampling phase.

1. Effective LSB Threshold Voltage on VIN,CM Variation

Fig. 11 shows the V${}_{\rm LSB,TH}$ on V${}_{\rm IN,CM}$ variation for Strong-ARM latch, double-tail, time-based, and the proposed comparator-based decision circuitries, respectively. In this work, all decision circuitries were set as ${\rm V}_{\rm LSB,TH} = 133.4$ mV at ${\rm V}_{\rm IN,CM} = 800$ mV. Then the Strong-ARM and double-tail structures have 406.9 mV and 527.7 mV of variations of V${}_{\rm LSB,TH}$, respectively, over V${}_{\rm IN,CM}$ = 500 mV through ${\rm V}_{\rm IN,CM} = 1.1$ V. In contrast, the proposed structure has 79.7 mV of variation. The variability of V${}_{\rm LSB,TH}$ of the proposed comparator depends on the common-mode-rejection capability of the linear pre-amplifiers, which can be improved by increasing the resistance of both M${}_{\rm DEGEN,1}$ and M${}_{\rm DEGEN,2}$.

The calculated V${}_{\rm LSB,TH}$ was compared with the simulation-based V${}_{\rm LSB,TH}$. For the calculation of V${}_{\rm LSB,TH}$, ${\rm V}_{\rm TAIL,avg} + {\rm V}_{\rm T}$ was assumed to be 450 mV for the conventional case and the average values of I${}_{\rm TAIL,1}$, I${}_{\rm TAIL,2}$, and g${}_{\rm m1,2}$ were taken from the transient simulation for the proposed case. In the conventional case, the two V${}_{\rm LSB,TH}$s agree well, and in the proposed case, they agree moderately due to the variabilities of each parameter on the time domain.

Fig. 11. Effective LSB threshold voltage on VIN,CM variation of Strong-ARM latch, double-tail, time-based, and proposed comparator-based decision circuitries.

2. BER of LSB on VIN,CM Variation

To show the BER of LSB of each decision circuitry, a test is set up as shown in Fig. 12. The MSB and LSB from the PRBS-15 generator were input to the PAM-4 modulator to generate the PAM-4 signal of 25 Gbps data rate. The signal was then passed through the channel with a loss of --3.886 dB at 6.25 GHz of Nyquist frequency. The full swing of the PAM-4 signal (V${}_{\rm IN,A}$ in Fig. 1) after passing through the channel is 200 mV.

Fig. 13 shows the BER test results from V${}_{\rm IN,CM} = 500$ mV through V${}_{\rm IN,CM} = 1.1$ V. The proposed structure has the widest bathtub width for ${\rm BER} = 10^{-4.5}$ (420 mV). In contrast, the conventional structures have widths of less than 230 mV. These results suggest that the proposed structure is most robust to input common level variation for LSB decisions.

The proposed dynamic comparator in Section IV was carefully designed and analyzed to ensure that the V${}_{\rm LSB,TH}$ has low variability. Therefore the V${}_{\rm LSB,TH}$ varied less over a wide V${}_{\rm IN,CM}$ range (Section V.1), which resulted in a low BER of LSB in that range.

Fig. 12. Testbench setup for BER of LSB simulation.

Fig. 13. BER of LSB on V$_{\rm IN,CM}$ variation of Strong-ARM latch, double-tail, time-based, and proposed dynamic comparator-based decision circuitries.

3. Delay for LSB Decision

For conventional decision circuitries, there is a comparator which is a bottleneck for LSB decision (shown in Fig. 3(a) with dashed lines). When V${}_{\rm IN,DM}$ is near V${}_{\rm LSB,TH}$, the comparator has the worst delay among other comparators for LSB decision. Figs. 14(a) and 14(b) show the delay of the comparators of each decision circuitry. The proposed comparator keeps a short delay at low V${}_{\rm IN,CM}$ (500 mV), similar to a double-tail comparator ^[7] because its structure is based on the form of the double-tail comparator.

The proposed structure does not need an XOR gate as a thermometer-to-gray decoder or any other back-end decoder (Fig. 12). Therefore, the proposed structure requires fewer stages for LSB decision than the other structures. Including the delays of the SR latch and XOR gate, the proposed structure has the shortest delay among them at moderate V${}_{\rm IN,CM}$ (800 mV) as shown in Fig. 14(c).

Fig. 14. Delay for LSB decision of Strong-ARM latch, double-tail, time-based, and proposed dynamic comparator-based decision circuitries.

4. Monte-Carlo Analysis

Fig. 15 shows the relation between positive and negative V${}_{\rm LSB,TH}$. In the ideal case, the difference between the values (${\rm V}_{\rm LSB,TH}{}^{+} -{\rm V}_{\rm LSB,TH}{}^{-}$) should be 0 V. However, an offset may occur in the ${\rm V}_{\rm LSB,TH}{}^{+} -{\rm V}_{\rm LSB,TH}{}^{-}$ due to PVT variation and mismatch. Fig. 16 shows the Monte-Carlo simulation results and how the offsets are distributed. 200 samples were taken for each decision circuitry. The standard deviations of the offsets are 10.5 mV, 37.9 mV, 25.3 mV, and 5.6 mV for Strong-ARM latch, double-tail, time-based, and proposed comparator-based decision circuitries, respectively. The simulation results show that the proposed structure is most tolerant of PVT variation and mismatch among them.

Fig. 15. Positive and negative effective LSB threshold voltage level and differential PAM-4 signal level.

Fig. 16. Monte-Carlo simulation results for offset of difference between positive and negative effective LSB threshold voltages of Strong-ARM latch, double-tail, time-based, and proposed comparator-based decision circuitries.

5. Comparison Table

A comparison of the conventional dynamic comparators and the proposed dynamic comparator is tabulated in Table 1. The energy required to decode both MSB and LSB is expressed as `Energy/conversion.' The proposed structure has the best performance with respect to V${}_{\rm LSB,TH}$ variation, BER of LSB, delay for LSB decision, and standard deviation of ${\rm V}_{\rm LSB,TH}{}^{+} -{\rm V}_{\rm LSB,TH}{}^{-}$.