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The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

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  4. 10.5573/JSTS.2025.25.2.166
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References

1 
H. Park, J. Sim, Y. Choi, J. Choi, Y. Kwon, and C. Kim, ``A 56-Gb/s PAM-4 receiver using time-based LSB decoder and S/H technique for robustness to comparator voltage variations,'' IEEE Journal of Solid-State Circuits, vol. 57, no. 2, pp. 562-572, Feb. 2022.DOI
2 
J. Sim, H. Park, Y. Choi, J. Choi, Y. Kwon, and C. Kim, ``PAM-4 receiver with 1-Tap DFE using clocked comparator offset instead of threshold voltages for improved LSB BER performance,'' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 5, pp. 1907-1916, May 2023.DOI
3 
K.-C. Chen, W. W.-T. Kuo, and A. Emami, ``60-Gb/s PAM4 wireline receiver with 2-tap direct decision feedback equalization employing track-and-regenerate slicers in 28-nm CMOS,'' IEEE Journal of Solid-State Circuits, vol. 56, no. 3, pp. 750-762, Oct. 2020.DOI
4 
A. Roshan-Zamir, T. Iwai, T.-H. Fan, A. Kumar, H.-W. Yang, and L. Sledjeski, ``A 56-Gb/s PAM4 receiver with low-overhead techniques for threshold and edge-based DFE FIR- and IIR-tap adaptation in 65-nm CMOS,'' IEEE Journal of Solid-State Circuits, vol. 54, no. 3, pp. 672-684, Mar. 2019.DOI
5 
T. Kobayashi, K. Nogami, T. Shirotori, Y. Fujimoto, and O. Watanabe, ``A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture,'' Proc. of IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 28-29, Jun. 1992.DOI
6 
B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, ``Yield and speed optimization of a latch-type voltage sense amplifier,'' IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, Jul. 2004.DOI
7 
D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, ``A double-tail latch-type voltage sense amplifier with 18ps setup+hold time,'' Proc. of IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pp. 314-605, 2007.DOI
8 
S. Babayan-Mashhadi and R. Lotfi, ``Analysis and design of a low voltage low-power double-tail comparator,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 343-352, Feb. 2014.DOI
9 
N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison-Wesley, Boston, MA, USA, Sec. 2.4.1, 2010.URL
10 
P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press, New York, NY, USA, Sec. 3.1, 2012.URL
11 
S. H. Hall and H. L. Heck, Advanced Signal Integrity for High-Speed Digital Designs, 1st ed., Wiley-IEEE Press, Hoboken, NJ, USA, 2009.URL
12 
W. J. Dally and J. W. Poulton, Digital Systems Engineering, 1st ed., Cambridge University Press, Cambridge, U.K., 1998.URL
13 
P. M. Figueiredo and J. C. Vital, ``Kickback noise reduction techniques for CMOS latched comparators,'' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 7, pp. 541-545, Jul. 2006.DOI
14 
B. Razavi, ``The strongARM latch: [A circuit for all seasons],'' IEEE Solid-State Circuits Magazine, vol. 7, no. 2, pp. 12-17, Mar. 2015.DOI
15 
H. Xu and A. A. Abidi, ``Analysis and design of regenerative comparators for low offset and noise,'' IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 2817-2830, Aug. 2019.DOI
16 
R. K. Siddharth, Y. J. Satyanarayana, Y. B. N. Kumar, M. H. Vasantha, and E. Bonizzoni, ``A 1-V, 3-GHz strong-arm latch voltage comparator for high speed applications,'' IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 2918-2922, Dec. 2020.DOI