I. INTRODUCTION

Currently, dynamic random-access memory (DRAM) is facing limitations in device reduction and performance improvement due to its structure including capacitors. Reducing the size of the capacitor leads to problems such as increased power consumption resulting from limited charge retention capacity, increased leakage current in high-temperature environments, and increased demand for data refresh. To solve these problems, capacitor-less DRAM (one-transistor DRAM, 1T-DRAM), which performs memory operations without capacitors, is attracting attention ^{[1,2,3,4,5,6,7,8,9]}. 1T-DRAM can perform memory functions with only a single transistor, making it easier to reduce the size of the device compared to existing DRAM ^{[10,11,12,13,14,15,16,17]}.

To maximize the performance of 1T-DRAM, optimization of device dimensions is essential. The dimensions of a device directly impact current flow, memory performance and data retention. By adjusting these dimensions, the memory's integration density can be increased, thereby achieving efficient performance ^[18,19]. Additionally, optimization using the transistor's zero-temperature coefficient (ZTC) point serves an important role in minimizing performance changes caused by temperature variations and maintaining consistent performance in various temperature environments^{[28,29,30,31,32]}. Setting the operation point is also an important factor in optimizing the performance of 1T-DRAM devices. Appropriate operation point setting maximizes data retention performance while enhancing memory performance and selecting the optimal operating point enhances device stability and ensures consistent performance under various conditions ^[20].

This study presents a method to design a memory device that can maintain reliability even in a high temperature environment by optimizing the device dimension and operation point of 1T-DRAM. By analyzing current-voltage ($I$-$V$) characteristics under various temperature conditions and proposing design techniques that minimize performance degradation using ZTC points, new approaches can be explored to overcome the limitations of existing DRAM and to maximize device performance and integration. Accordingly, a foundation will be established to contribute to the development of next-generation memory devices with high reliability against temperature variations.

II. DEVICE STRUCTURE

Fig. 1 shows the cross-sectional view of the 1T-DRAM, which is designed with an asymmetric dual-gate structure to optimize characteristics regarding memory performance and data retention ^{[21,22,23,24]}. The main gate (gate 1) primarily controls the current flow within the channel, facilitating the switching operations between “write” and “read” states. Meanwhile, the control gate (gate 2) is designed with a high work function to maintain a consistent charge in the body region, thereby ensuring data stability.

The structural parameters of the 1T-DRAM presented in Table 1 are critical factors influencing device performance, and these conditions were analyzed through TCAD simulation ^[25]. The lengths of gate 1 and gate 2 were set to 100 nm and 70 nm. The body thickness was designed to be 17 nm, which serves as the charge storage region. The thin channel thickness enables high-speed switching and high memory performance, thereby improving data retention time. Additionally, the oxide thickness was designed to be 3 nm, ensuring insulation between the gate and the channel and enabling efficient channel control through gate voltage. The source and drain regions were doped with N-type silicon, while the body region was doped with P-type silicon. The work function of the main gate (WF1) was set to 4.6 eV-5.1 eV, and that of the control gate (WF2) was set to 5.1 eV. WF1 and body doping were prioritized over other parameters in this study, as they are directly associated with the current-voltage ($I$-$V$) characteristics, thermal stability, and memory performance of the device, enabling the optimization of its operation.

III. RESULTS AND DISCUSSION

The ZTC point is the gate voltage at which current variation due to temperature changes is minimized ^[28,31], serving as a critical reference point that reduces the temperature sensitivity of the device and ensures stable performance even at high temperatures. Previous studies applied the ZTC concept to analyze the current-voltage characteristics of 1T-DRAM under temperature variations and confirmed that memory operation at the ZTC point remained stable despite temperature changes ^[20]. These studies demonstrated that the ZTC point serves as a crucial reference for ensuring reliable operation even at high temperatures. In this study, the ZTC concept is utilized to minimize drain current fluctuations in 1T-DRAM depending on device parameters and to ensure stable operation even in high-temperature environments (300 K-400 K).

Fig. 2 shows the drain current characteristics as a function of gate voltage under various temperature conditions (300 K-400 K) and WF1, which are shown in both linear and log scales. In Fig. 2(a), the shift of the ZTC point with changes in WF1 can be observed. At the ZTC point, the current is hardly affected by temperature variations. However, before and after the ZTC point, the current characteristics vary with temperature changes ^[26]. Before the ZTC point, as the temperature increases, the carrier concentration rises due to thermal generation effects, resulting in a higher drain current value. In contrast, beyond the ZTC point, as the temperature rises, the increase in phonon scattering decreases carrier mobility, resulting in a reversal phenomenon where the current reduces. The reversal phenomenon can cause instability in memory operation within a specific range, potentially degrading data retention performance at high temperatures.

In Fig. 2(a), as the ZTC point shifts to the right, the threshold voltage also shifts to the right, resulting in the device operating at a higher operation point. In contrast, as the ZTC point shifts to the left, the threshold voltage also shifts to the left, lowering the operation point. The shift of the ZTC point alters the operating voltage range of the device, and this change directly impacts memory performance in practical environments. However, even if the ZTC point shifts, the device can operate stably at this point without being significantly affected by temperature variations. Therefore, the location of the ZTC point serves as a critical design factor with respect to the device's memory operation efficiency and stability.

Fig. 2(b) shows the changes observed in the off-current state. The off-current refers to the drain current flowing when the gate voltage is 0 V, and its value increases as the WF1 value decreases. This is because the energy barrier is lowered, allowing charges to leak more easily, which can significantly affect the retention time of the memory along with a reduction in the threshold voltage. Therefore, it is essential to optimize the WF1 value by considering the off-current variations induced by temperature changes.

Fig. 3 shows the impact of WF1 and body doping concentration variations on the ZTC point. As the WF1 value increases, the ZTC point generally rises. Notably, when WF1 is above 4.8 eV, the ZTC point remains almost identical for body doping concentrations of $1 \times 10^{16}$ cm${}^{-3}$ and $1 \times 10^{17}$ cm${}^{-3}$. This phenomenon occurs because a high WF1 value compensates for the variations in mobility and threshold voltage caused by temperature changes, thereby stabilizing the position of the ZTC point ^[33]. However, when the body doping concentration increases to $1\times 10^{18}$ cm$^{-3}$, the ZTC point tends to rise. At high body doping concentrations, the electric field within the channel is intensified, resulting in a significant reduction in mobility. To compensate for this, the threshold voltage increases, thereby causing the ZTC point to rise. When the WF1 value is below 4.8 eV, the compensation between the temperature-dependent effects of mobility and threshold voltage is insufficient, resulting in the ZTC point not remaining consistent.

In Fig. 2, the temperature range of 300 K to 400 K was analyzed to investigate the transfer characteristics under varying thermal conditions. In contrast, the measurements in Fig. 4 were conducted for memory characteristic analysis, with the high-temperature condition set to 358 K ($= 85^\circ{C}$), a commonly referenced evaluation point in evaluations of DRAM retention characteristics.

Fig. 4(a) shows the voltage range of 0.9 V to 1.4 V, which represents the gate voltage (${R}_{\_\rm vg1}$) in the read state, and this range was set to evaluate memory performance under various gate voltage conditions of the 1T-DRAM. The memory characteristics were analyzed using the 1T- when WF1 was 4.7 eV and the body doping concentration was $1 \times 10^{17}$ cm${}^{3-}$. DRAM memory operating voltage conditions are presented in Table 2. The program (write ``1'') phase utilizes the band-to-band tunneling (BTBT) phenomenon. In this phenomenon, electron-hole pairs are generated between the conduction band and the valence band when a high electric field is induced by the gate voltage <sup>[27]</sup>. During this phase, the concentration of holes formed through BTBT is a critical factor in determining the sensing margin. In the ``1'' state, numerous holes are generated through BTBT and accumulate in the body region under gate 2, maintaining a high current. In contrast, in the ``0'' state, BTBT occurs very limitedly, resulting in a lower hole concentration and maintaining a low current. The difference in drain current between the read ``1'' state and the read ``0'' state is referred to as the sensing margin, which serves as a critical metric for evaluating memory performance. The sensing margin at a gate voltage of 1.1 V was 12.549 $\mu$A, confirming that the memory operates normally (${T }= 300$ K). Additionally, the drain current variations were observed under the given temperatures (300 K, 358 K) as a function of the gate voltage ($R_{\_\rm vg1}$) in the read state. The sensing margin varies depending on temperature and gate voltage conditions, and a reversal in current values between the read ``1'' and read ``0'' states can be observed at 300 K and 358 K within a specific voltage range.

Fig. 4(b) shows the drain current variations of the read ``1'' and ``0'' states as a function of gate voltage ($R_{\_\rm vg1}$) at temperatures of 300 K and 358 K. The arrows in the figure are used to highlight the current values within the specified voltage range and display an enlarged graph, clearly illustrating the differences in memory operation characteristics with respect to temperature. In the region where the gate voltage ($R_{\_\rm vg1}$) is at or below 0.9 V, it can be observed that the read ``0'' value at 358 K is nearly identical to the read ``1'' value at 300 K. However, in the region where the gate voltage ($R_{\_\rm vg1}$) is above 1.4 V, the read ``0'' value at 300 K is greater than the read ``1'' value at 358 K. This phenomenon occurs due to variations in drain current caused by temperature changes. This reversal phenomenon, where the read ``0'' value is greater than the read ``1'' value, is a cause of reduced stability in memory operation within specific regions. Therefore, it is crucial to define the optimal range of gate voltage ($R_{\_\rm vg1}$) to maximize the stability of the memory device.

The sensing margin and reversal phenomenon observed in Fig. 4 are further analyzed through the electron density and mobility distributions shown in Fig. 5. Fig. 5 shows the variations in electron density and mobility during the read operation in the 1T-DRAM, clearly presenting the differences in physical phenomena before and after the ZTC point ($= 1.15$ V).

Fig. 5(a) shows the electron density distribution in the region before the ZTC point, comparing the read ``1'' state at 300 K and the read ``0'' state at 358 K when the gate voltage ($R_{\_\rm vg1}$) in the read state is 0.9 V. In the read ``1'' state, the electron density within the channel remains uniform, whereas in the read ``0'' state, the electron density significantly increases inside the channel due to thermal generation effects, leading to a higher current value and causing a reversal phenomenon where it exceeds the read ``1'' value.

Fig. 5(b) shows the electron density distribution comparing the read ``1'' and read ``0'' states at 358 K when the gate voltage ($R_{\_\rm vg1}$) in the read state is 1.1 V. In this region, the electron density within the channel is higher in the read ``1'' state than in the read ``0'' state, indicating that no reversal phenomenon occurs and the device remains in a normal state.

Fig. 5(c) shows the electron mobility distribution for the read ``1'' state at 358 K and the read ``0'' state at 300 K when the gate voltage in the read state is 1.4 V. In the read ``0'' state, the electron mobility density is higher than in the read ``1'' state, resulting in a larger current value and causing a reversal phenomenon. The reversal phenomenon demonstrates the differences in physical phenomena, such as thermal generation effects and changes in electron mobility, before and after the ZTC point, providing valuable insights for evaluating the stability and performance of memory devices.

The gate voltages ($R_{\_\rm vg1}$) used in Figs. 6 and 7 are summarized in Table 3. These values were determined based on the ZTC point of each parameter condition. The measurements in Figs. 6 and 7 were conducted using these optimal read voltages.

Fig. 6(a) and (b) show how the drain current changes over time at temperatures of 300 K and 358 K, respectively, when the WF1 value and body doping concentration are varied. The data state of the 1T-DRAM utilizes the characteristic that the hole concentration is high in the read ``1'' state and low in the read ``0'' state. The read operation was performed at the ZTC point, and it was confirmed that ``1'' and ``0'' are clearly distinguishable.

Fig. 6(c) shows the changes in sensing margin depending on WF1 and body doping concentration. The sensing margin increases with the rise in WF1 and reaches its peak value at WF1 = 4.9 eV. However, when WF1 increases to 5.0 eV or higher, the electric field weakens. This reduction in the electric field causes a decrease in the BTBT phenomenon. As a result, the hole generation rate drops, which reduces the current difference between the read ``1'' and ``0'' states and lowers the sensing margin.

The body doping concentration is a key parameter related to the body characteristics of 1T-DRAM, serving a crucial role in controlling hole generation. At low doping concentrations, the depletion region widens, and the electric field weakens, potentially limiting hole generation through the BTBT phenomenon. As a result, the sensing margin is reduced. This makes it difficult to reliably distinguish between data states. At higher doping concentrations, the depletion region becomes narrower, and the electric field intensifies, enhancing the BTBT phenomenon and increasing the sensing margin. Consequently, by optimally setting WF1 and body doping concentration, the sensing margin and data stability can be maximized.

Figs. 7(a)-7(c) show the data retention characteristics of the 1T-DRAM as a function of WF1 values and demonstrate the impact of the asymmetric double-gate structure's design characteristics on data retention time. The depletion region formed between gate 1 and gate 2 in this structure suppresses hole recombination and effectively retains holes, enhancing data stability.

In Fig. 7(a), the read ``1'' state current of the 1T-DRAM with a WF1 of 4.6 eV declines sharply after around 30 ms. This is attributed to the reduction of the depletion region at lower WF1 values, which is insufficient to inhibit hole recombination. Therefore, holes cannot be retained for a prolonged period, which results in shorter data retention time and makes it difficult to reliably distinguish data states. As the WF1 value increases, the depletion region expands. This expansion effectively suppresses hole recombination. As a result, the current in the read ``1'' state remains stable for approximately 70 ms in Fig. 7(b), improving the distinction and stability of data states.

In Fig. 7(c), the WF1 value significantly increases, leading to the sufficient formation of the depletion region. This depletion region strongly suppresses the recombination of holes and electrons, allowing the current in the read ``1'' state to remain stable for approximately 330 ms. All preceding results were obtained using the ZTC point as the operating voltage condition for the read operation, confirming a clear distinction between the read ``1'' and ``0'' states. Furthermore, retention characteristics were successfully achieved under these conditions.

Fig. 8 shows the variation in retention time of the 1T-DRAM as a function of WF1. As the WF1 value increases, a tendency for longer retention time can be observed. This is because a higher WF1 value strengthens the electric field formed by gate 1, which increases the generation of holes. The generated holes are suppressed from recombining due to the depletion region and are stably retained in the body region beneath gate 2. At WF1 $= 4.6$ eV, the retention time is short at approximately 30 ms, while it increases steadily as the WF1 value rises. At WF1 $= 5.1$ eV, the retention time reaches approximately 550 ms, and this further improves data retention characteristics. However, if the WF1 value becomes excessively high, the sensing margin may decrease, and this makes it more difficult to distinguish data states.

IV. CONCLUSIONS

In this study, an asymmetric dual-gate 1T-DRAM device structure was designed to demonstrate that data stability and reliability can be ensured even in high-temperature environments. By optimizing the operating voltage based on the ZTC point, stable operation was achieved under various temperature conditions (300 K-400 K). Additionally, the optimization of WF1 and body doping concentration effectively controlled data retention time and stability. Notably, when WF1 was set to 4.7 eV, a data retention time of 70 ms was achieved, maximizing stability. Furthermore, at WF1 = 5.0 eV, a long retention time of 330 ms was secured, suggesting the potential for application under specific conditions such as high-temperature environments. This provides a design direction that can flexibly adjust the trade-off between data stability and performance.