1. Microarchitectural Fault Analysis

To evaluate the impact of faults on accuracy degradation in output-stationary systolic array architectures, we define $D_{\rm fault}$ as the distance from the array boundary---where in- put data is initially supplied---to the pro cessing element (PE) at which the fault occurs, as illustrated in Fig. 1(c).

This parameter allows us to quantify the spatial propagation of faults within the systolic array. Our microarchitectural analysis considers multiple fault-related parameters, including the fault type, bit index, faulty PE rate (FPR), and the aforementioned $D_{\rm fault}$.

The experimental setup for the fault analysis is as follows. We perform fault injection on a $16 \times 16$ systolic array using the MNIST dataset ^[19]. Permanent faults ranging from 1-bit to 16-bit are injected into the 8-bit registers that receive data from neighboring PEs. Accordingly, the bit index spans from 1 (least significant bit, LSB) to 8 (most significant bit, MSB). To simulate worst-case conditions at the microarchitectural level, we assume that all other system components are operating under the most disadvantageous settings, except for the comparison group under evaluation. This setup ensures that we can isolate and clearly observe the individual effects of each fault parameter.

We compute the accuracy degradation using the Mean Absolute Percentage Error (MAPE), and we record both the maximum and minimum observed degradations along with their corresponding parameter settings. As shown in Table 1, faults of the Stuck-at-1 type result in approximately 23% greater accuracy degradation compared to Stuck-at-0 faults. This disparity may be attributed to the asymmetry in value distributions within activation functions like ReLU, which tend to suppress negative outputs and amplify positive ones.

Moreover, faults at the MSB level cause significantly greater degradation than those at the LSB level---by up to 46.7%---highlighting the critical influence of bit significance in fixed-point arithmetic. Similarly, increasing the number of injected faults from 1 to 16 results in a 21.5% rise in error rates, indicating the cumulative effect of fault density. Spatially, faults closer to the input boundary ($D_{\rm fault} = 0$) cause approximately 29.1% more degradation than those occurring at the farthest boundary ($D_{\rm fault} = 15$), which supports the hypothesis that early-stage faults propagate more aggressively through the systolic flow.

Among the evaluated parameters, the bit index and $D_{\rm fault}$ emerged as the most dominant contributors to ac- curacy degradation. Accordingly, we target these two fac- tors in our proposed mitigation techniques. The HL-Swap mechanism addresses bit-level sensitivity by redirecting high-bit values to low-bit locations, while the RC-Off technique mitigates spatial fault propagation by selectively disabling critical rows or columns based on fault severity analysis.

Fig. 1. Motivation of fault-tolerant GEMM accelerator: (a) accuracy degradation due to permanent faults and transient faults, (b) limitations of previous works, and (c) accuracy drop with two major fault factors.

Table 1. Microarchitectural fault analysis: Impact of fault factors on accuracy drop with MNIST.

2. HL-Swap: High-Low Bit Swapping

According to the fault analysis described earlier, computational accuracy can degrade by up to 50.2% depending on the bit index where the fault occurs. In particular, faults at higher bit positions have a significantly greater impact on the output compared to lower bits, as higher bits carry more weight in fixed-point arithmetic. To address this issue, we propose a fault mitigation technique called HL-Swap, which is designed to reduce the impact of bit-index-dependent faults. HL-Swap operates by exchanging the upper bits with the lower $e$ bits in a register when a fault is detected in the upper half. More specifically, as illustrated in Fig. 2, when on of the two 8-bit registers receiving data from neigh boring PEs encounters a fault in its upper 4 bits, HL-Swap swaps them with the lower 4 bits within the same register. After the swap, a shifter realigns the data path to ensure that the accumulation process functions correctly despite the modified bit positions.

HL-Swap supports four operational modes depending on the location of the fault: No Swap, Reg0 Swap, Reg1 Swap, and Reg0,1 Swap. The No Swap mode is selected when no fault is present or when only the lower 4 bits are affected. Reg0 Swap is applied when the upper 4 bits of Reg0 are faulty, while Reg1 Swap is used if the upper 4 bits of Reg1 are affected. Reg0,1 Swap is activated when faults exist in the upper 4 bits of both Reg0 and Reg1.

These swap modes enable adaptive fault handling based on the location of the fault, and the mechanism provides effective mitigation without requiring redundant hard- ware. By using only simple internal bit manipulation and a lightweight shifter, HL-Swap offers a practical solution with minimal area overhead while preserving computational accuracy.

Fig. 2. Proposed HL-Swap fault mitigation method operation scheme.

3. RC-Off: Location-Aware Row-Column Off with Scoring

As illustrated in Fig. 3, we propose a fault mitigtion mechanism called RC-Off, which selectively deactivates specific rows or columns in the systolic array based on their estimated contribution to accuracy degradation. Unlike conventional redundancy-based methods that uniformly replicate resources regardless of fault severity, RC- Off dynamically adapts its response according to the microarchitectural location and fault characteristics. This al lows the system to avoid unnecessary overhead while effectively suppressing high-impact faults. The method operates through three distinct phases: fault analysis, monitoring, and adaptive handling.

In the first phase, an offline fault analysis is conducted to assess the correlation between fault-induced degradations and their spatial and logical properties. Since accuracy degradation is highly sensitive to both the AI model architecture and the dataset in use, this phase begins by injecting faults into the systolic array under controlled conditions. We simulate various fault types, bit indices, positions, and quantities to build a comprehensive characterization. The results are aggregated into a score table that captures how much each fault configuration impacts output accuracy. This score table serves as a statistical foundation for runtime decision-making.

In the second phase, real-time monitoring is activated. Upon fault detection, each row and column in the systolic array is assigned a fault severity score. This score is computed based on the predefined score table and the attributes of the detected faults, including their type, bit position, spatial distance from the array boundary, and frequency. The scoring policy is defined as

In this equation, ${n} $ indexes each detected fault, ${ft} $ reprsents the fault type (e.g., stuck-at-0, stuck-at-1), ${bi} $ is the bit index within the register, ${d} $ corresponds to the fault distance $D_{\rm fault}$, and ${num} $ is the total number of faults observed in the given row or column. Each term is weighted according to its relative influence on output degradation, based on prior analysis.

In the final phase, once a row or column exceeds a predefined score threshold---indicating that it significantly degrades system accuracy---it is selectively disabled. This is implemented through a binary enable signal: a value of 1 maintains normal operation, while 0 indicates that the row or column is excluded from subsequent computations. The input data fed into the systolic array is dynamically reshaped to bypass these disabled elements, ensuring consistent data flow and structural integrity. This design ensures that computational resources are efficiently reallocated and fault impact is minimized without requiring full redundancy or complex reconfiguration logic.

Overall, RC-Off enables location-aware and model- sensitive fault mitigation, achieving a favorable balance between reliability and resource efficiency. The simplicity of its runtime enforcement makes it suitable for deployment in edge systems where area and power constraints are stringent.

Fig. 3. Overall scheme of the proposed RC-Off fault mitigation method based on the microarchitectural location of faults.

4. Fault-Tolerant GEMM Accelerator

The accelerator consists of a systolic array, SRAM buffer, data reshaper, Score Table, and Fault Monitor. It employs four $16\times 16$ systolic arrays for computation.

To mitigate the accuracy drop incurred by the most significant fault factor, bit index, as shown in Fig. 1(c), HL- Swap is applied to convert faulty high-bit registers to fault- free low-bit registers. Also, to support RC-Off, the pro- posed GEMM accelerator measures the accuracy degradation rate based on the microarchitectural location and type of fault occurrence, which is stored in the score table as depicted in Fig. 4. The fault monitor continuously computes severity scores for RC-Off, bypassing them if the score exceeds a threshold value. This proposed approach effectively mitigates the impact of the propagation chain in the systolic array. In this scenario, erroneous data not only affects the faulty PEs but also spreads to other PEs when a permanent fault occurs in a PE.

The SRAM buffer preloads data to enhance data re- trieval efficiency. The data reshaper adjusts systolic array data feeding according to RC-Off criteria to mitigate accuracy drop. The score table updates fault-related information injected via fault injection commands and accommodates changes in fault bit indices through HL-Swap. The fault monitor computes fault severity based on the score table.

Fig. 4. Overall architecture of proposed fault-tolerantsystolic array for GEMM accelerator.