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REFERENCES

1 
Lin J.-T., Lin H.-H., Chen Y.-J., Yu C.-Y., Kranti A., Lin C.-C., Lee W.- H., Dec 2017, Vertical Transistor With n-Bridge and Body on Gate for LowPower 1T-DRAM Application, in IEEE Trans. On Electron Devices, Vol. 64, No. 12, pp. 4937-4945DOI
2 
Ansari M. H. R., Navlakha N., Lin J.-T., Kranti A., Mar 2018, Doping dependent assessment of accumulation mode and junctionless FET for 1T DRAM, IEEE Trans. Electron Devices, Vol. 65, No. 3, pp. 1205-1210DOI
3 
Ansari M. H. R., Navlakha N., Lin J.-T., Kranti A., Jul 2018, High retention with n-oxide-p junctionless architecture for 1T DRAM, IEEE Electron Device Lett., Vol. 65, No. 7, pp. 2797-2803DOI
4 
Parihar M. S., Lee K. H., El Dirani H., Navarro C., Lacord J., Martinie S., Barbe J.-C., Fonteneau P., Galy P., Le Royer C., Mescot X., Gamiz F., Cheng B., Asenov A., Taur Y., Bawedin M., Cristoloveanu S., May 2017, Low-power Z2-FET capacitorless 1T-DRAM, in Proc. IEEE Int. Memory Workshop (IMW), pp. 1-4DOI
5 
Gamiz F., Rodriguez N., Marquez C., Navarro C., Cristoloveanu S., Oct 2014, A2RAM: Low-power 1T-DRAM memory cells compatible with planar and 3D SOI substrates, in Proc. IEEE Int. Memory Workshop (IMW), pp. 1-4DOI
6 
Navlakha N., Lin J.-T., Kranti A., Sep 2016, Improved retention time in twin gate 1T DRAM with tunneling based read mechanism, IEEE Electron Device Lett., Vol. 37, No. 9, pp. 1127-1130DOI
7 
Han D. C., Jang D. J., Cho S., Cho I. H., Jul 2019, Investigation of modified 1T-DRAM with twin gate tunneling field effect transistor for improved retention characteristics, in Proc. AWAD 2-19, pp. 179-180Google Search