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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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REFERENCES

1 
Yin B., Wei X., April 2019, Communication-Efficient Data Aggregation Tree Construction for Complex Queries in IoT Applications, IEEE Internet of Things Journal, Vol. 6, No. 2, pp. 3352-3363DOI
2 
Wang J., Gao Y., Liu W., 2019, An intelligent data gathering schema with data fusion supported for mobile sink in wireless sensor networks, International Journal of Distributed Sensor Networks, Vol. 15, No. 3, pp. 1-9DOI
3 
Wang J., Gao Y., Yin X., 2018, An Enhanced PEGASIS Algorithm with Mobile Sink Support for Wireless Sensor Networks", Wirel. Commun. Mob. Comput., vol. 2018, Article ID 9472075, 2018., Wirel. Commun. Mob. Comput., Vol. 2018, No. Article ID 9472075DOI
4 
Li W., Chen Z., Gao X., 2019, Multi-Model Framework for Indoor Localization under Mobile Edge Computing Environment, IEEE Internet Things J., Vol. 6, pp. 4844-4853DOI
5 
Wang J., Gao Y., Liu W., Wu W., 2019, An Asynchronous Clustering and Mobile Data Gathering Schema based on Timer Mechanism in Wireless Sensor Networks, CMC Comput. Mater. Contin. 2019, Vol. 58, pp. 711-725Google Search
6 
Zhang J. L., Shen C., Su H., Arafin M. T., Qu G., 2021, Voltage Over-scaling-based Lightweight Authentication for IoT Security", IEEE Transactions on Computers, 2021, IEEE Transactions on ComputersDOI
7 
Wang W., Wang X., Wang J., Xiong N. N., Cai S., Liu P., 2020, Ensuring Cryptography Chips Security by Preventing Scan-Based Side Channel Attacks With Improved DFT Architecture, IEEE Transactions on Systems Man Cybernetics-SystemsDOI
8 
Zhang J. L., Wang W. Z., Wang X. W., Xia Z. H., Mar. 2017, Enhancing security of FPGA-based embedded systems with combinational logic binding", J. Comput. Sci. Technol., Vol. 32, No. 2, pp. 329-339DOI
9 
Zhang J., Qu G., Aug 2020, Physical Unclonable Function-based Key-Sharing via Machine Learning for IoT Security, IEEE Transactions on Industrial Electronics, Vol. 67, No. 8, pp. 7025-7033DOI
10 
Ali S. S., Sinanoglu O., Karri R., 2014, Test-mode-only scan attack using the boundary scan chain, in Proc. 19th IEEE Eur. Test Symp. (ETS), Vol. paderborn, No. germany, pp. 1-6DOI
11 
Tehranipoor M., Wang C., 2011, Introduction to Hardware Security and Trust, New York, Vol. ny, No. USA: SpringerGoogle Search
12 
Yang B., Wu K., Karri R., 2004, Scan-based side-channel attack on dedicated hardware implemen-tations of data encryption standard, in Proc. Int. Test Conf. (ITC), Washington, DC, USA, pp. 339-344DOI
13 
Nara R., Togawa N., Yanagisawa M., Ohtsuki T., jan. 2010, Scan-based attack against elliptic curve cryptosystems, in Proc. Asia South Pacific Design. Autom. Conf. (ASPDAC), Vol. taipei, No. taiwan, pp. 407-412DOI
14 
Yang B., Wu K., Karri R., Oct 2006, Secure scan: A design-for-test archi tecture for Crypto chips, IEEE Trans. Comput.-Aided Design Integr., Vol. 25, No. 10, pp. 2287-2293DOI
15 
Nara R., Satoh K., Yanagisawa M., Togawa N., Commun Comput Sci, Scan-based side channel attack against RSA cryptosystems using scan signatures, IEICE Trans. Fundam. Electron., Vol. E93-A, No. 12, pp. 2481-2489DOI
16 
Kömmerling O., Kuhn M. G., may 1999, Design principles for tamper-resistant smartcard processors, in Proc. USENIX Workshop Smartcard Technology, Vol. chicago, No. il, pp. 9-20Google Search
17 
Josephson D., Poehhnan S., 2001, Debug methodology for the McKinley processor, in Proc. Int. Test Conf., Vol. baltimore, No. md, pp. 451-460DOI
18 
Hafner , 1991, Design and test of an integrated cryptochip, IEEE Design and Test of Computers, pp. 6-17DOI
19 
Zimmermann , Mar 1994, A 177 Mbit/s VLSI Implementation of the International data Encryption System, IEEE Journal of Solid-State Circuits, Vol. 29, No. 3DOI
20 
Paul S., Chakraborty R. S., Bhunia S., May 2007, Vim-Scan: A low overhead scan design approach for protection of secret key in scan-based secure chips, in Proc. 25th IEEE VLSI Test Symp., Vol. Berkeley, No. CA, USA, pp. 455-460DOI
21 
Yu T., Cui A., Li M., Ivanov A., may 2015, A new decompressor with ordered parallel scan design for reduction of test data and test time, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Vol. lisbon, No. portugal, pp. 641-644DOI
22 
Liu C., Huang Y., May 2007, Effects of embedded decompression and compaction architectures on side-channel attack resistance, in Proc. 25th IEEE VLSI Test Symp. (VTS), Vol. Berkeley, No. CA, USA, pp. 461-468DOI
23 
Da Rolt J., Di Natale G., Flottes M.-L., Rouzeyre B., oct. 2013, A novel differential scan attack on advanced DFT structures, ACM Trans. Design. Autom. Electron. Syst., Vol. 18, No. 4DOI
24 
Cui A., Chang C. H., Zhou W., Zheng Y., A New PUF Based Lock and Key Solution for Secure In-field Testing of Cryptographic Chips, IEEE Transactions on Emerging Topics in Computing.DOI
25 
Cui A., Luo Y., Chang C., Feb 2017, Static and Dynamic Obfuscations of Scan Data Against Scan-Based Side-Channel Attacks, IEEE Transactions on Information Forensics and Security, Vol. 12, No. 2, pp. 363-376DOI
26 
Oct. 2014, AES: Overview. [Online]. Available: http://opencores.org/project,tiny_aesGoogle Search
27 
Verbauwhede I., Schaumont P., Kuo H., Mar 2003, Design and performance testing of a 2.29-GB/s Rijndael processor, IEEE J. Solid-State Circuits, Vol. 38, No. 3, pp. 569-572DOI
28 
Hely D., Bancel F., Flottes M.-L., Rouzeyre B., may 2005, Test control for secure scan designs, in Proc. Eur. Test Symp. (ETS), Vol. tallinn, No. estonia, pp. 190-195DOI
29 
Luo Y., Cui A., Qu G., Li H., may 2016, A new countermeasure against scan based side-channel attacks, in Proc. 2016 IEEE Int. Symp. Cir. Syst., Vol. montreal, No. canada, pp. 1722-1725DOI
30 
Atobe Y., Shi Y., Yanagisawa M., Togawa N., dec. 2012, State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit, in Proc. IEEE Asia Pacific Conf. Circuit. Syst. (APCCAS), Vol. kaohsiung, No. taiwan, pp. 607-610DOI
31 
Ali S. S., Sinanoglu O., Saeed S. M., Karri R., 2013, New scan-based attack using only the test mode, in Proc. IFIP/IEEE 21st Int. Conf. Very Large Scale Integr. (VLSI SoC), pp. 234-239DOI
32 
Wang X., Zhang D., He M., Su D., Tehranipoor M., Sept 2018, Secure Scan and Test Using Obfuscation Throughout Supply Chain, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 37, No. 9, pp. 1867-1880DOI
33 
Xiang D., Li K., Sun J., Fujiwara H., 2007, Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction, IEEE Transactions on Computers, Vol. 56, No. 4, pp. 557-562DOI
34 
Park K., Yoo S.G., 2010, JTAG Security System Based on Credentials, Journal of Electronic Testing, Vol. 26, No. 5, pp. 549-557DOI