Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2024-02 (Vol.24 No.01)
  4. 10.5573/JSTS.2024.24.1.1
XML PDF INFO REF

References

1 
Y. Ren, X. Yang, L. Zhou, J.-Y. Mao, S.-T. Han, and Y. Zhou, “Recent Advances in Ambipolar Transistors for Functional Applications,” Adv. Funct. Mater., vol. 29, no. 40, Jul. 2019, Art. no. 1902105.DOI
2 
J. Zaumseil and H. Sirringhaus, “Electron and ambipolar transport in organic field-effect transistors,” Chem. Rev., vol. 107, pp. 1296-1323, Mar. 2007.DOI
3 
S. Z. Bisri, C. Piliego , J. Gao, and M. A. Loi, “Outlook and emerging semiconducting materials for ambipolar transistors,” Adv. Mater., vol. 26, pp. 1176-1199, Feb. 2014.DOI
4 
Y. Zhang, C.-H. Huang, and K. Nomura, “Voltage transfer characteristics of CMOS-like inverters for ambipolar SnO thin-film transistors,” IEEE Electron Device Lett., vol. 43, no. 1, pp. 52-55, Jan. 2022.DOI
5 
J.-S Jang and W. Y. Choi, “Ambipolarity factor of tunneling field-effect transistors (TFETs),” J. Semicond. Technol. Sci., vol. 11, no. 4, pp. 272-277, Dec. 2011.URL
6 
F. Mayer et al., “Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance,” in IEEE Int. Electron Devices Meet., San Francisco, CA, USA, 2008, pp. 162-166.DOI
7 
A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,” Proc. IEEE, vol. 98, no. 12, pp. 2095-2110, Dec. 2010.DOI
8 
W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. King Liu, “Tunneling field effect transistors (TFETs) with subthreshold swing (SS) less than 60 mv/dec,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 743-745, Aug. 2007.DOI
9 
A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329-337, Nov. 2011.DOI
10 
N. Patel, A. Ramesha, and S. Mahapatra, “Drive current boosting of n-type tunnel FET with strained SiGe layer at source,”, Microelectron. J., vol 39, no. 12, pp. 1671-1677, Dec. 2008.DOI
11 
Sentaurus Device User Guide, Version T-2022.03, Synopsys, Inc., Mountain View, CA, USA, 2022.URL
12 
K.-H. Kao, A. S. Verhulst, W. G. Vandenberghe, B. Sorée, G. Groeseneken, and K. De Meyer, “Direct and indirect band-to-band tunneling in germanium-based TFETs,” IEEE Trans. Electron Devices, vol. 59, no. 2, pp. 292-301, Feb. 2012.DOI
13 
J.-H Han, M. Takenaka, and S. Takagi, “Analysis of interface trap density of plasma post-nitrided Al2O3 /SiGe MOS interface with high Ge content using high-temperature conductance method,” J. Appl. Phys., vol. 120, no. 12, Sep. 2016, Art. no. 125707.DOI
14 
D. J. Paul, “Si/SiGe heterostructures: from material and physics to devices and circuits,” Semicond. Sci. Technol., vol. 19, no. 10, pp. R75-R108, Oct. 2004.DOI
15 
M. Arienzo, S. S. Iyer, B. S. Meyerson, G. L. Patton, and J. M.C. Stork, “Si-Ge alloys: growth, properties and applications,” Appl. Surf. Sci., vol. 48/49, pp. 377-386, 1991.DOI
16 
P.-E. Hellberg, S.-L. Zhang, F. M. d’Heurle, and C. S. Petersson, “Oxidation of silicon-germanium alloys. I. An experimental study,” J. Appl. Phys., vol. 82, no. 11, pp. 5773-5778, Dec. 1997.DOI
17 
C. H. Lee et al., “Selective GeOx-scavenging from interfacial layer on Si1-xGex channel for high mobility Si/Si1-xGex CMOS application,” in IEEE Symp. VLSI Technol., Honolulu, HI, USA, 2016, pp. 1-2.DOI
18 
H. Lu, D. Esseni, and A. Seabaugh, “Universal analytic model for tunnel FET circuit simulation,” Solid-State Electron., vol. 108, pp. 110-117, Jun. 2015.DOI
19 
HSPICE User Guide: Simulation and Analysis P-2019.06, Synopsys. Inc., Mountain View, CA, USA, Jun. 2008.URL
20 
H. Lu, T. Ytterdal, and A. Seabaugh, Notre Dame TFET Model (Version 2.1.0), nanoHUB, 2017.URL
21 
A. Pal, A. B. Sachid, H. Gossner, and V. R. Rao, “Insights into the design and optimization of tunnel-FET devices and circuits,” IEEE Trans. Electron Devices, vol. 58, no. 4, pp. 1045-1053, Apr. 2011.DOI
22 
S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan, “On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors,” IEEE Electron Device Lett., vol. 30, no. 10, pp. 1102-1104, Oct. 2009.DOI