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References

1 
B. Gassend, et al, “Silicon physical random functions,” Computer and Communications Security, 2002. CCS 2002, Proceedings of the ACM Conference on, pp. 148-160, Nov., 2002.DOI
2 
G. Vaidya and T. Prabhakar, “Hardware based identification for Intelligent Electronic Devices,” 2022 IEEE/ACM Seventh International Conference on Internet-of-Things Design and Implementation (IoTDI), 2022.DOI
3 
C. Herder, et al, “Physical Unclonable Functions and Applications: A Tutorial,” IEEE, Proceedings of, Vol. 102, No. 8, pp. 1126-1141, May, 2014.DOI
4 
L. Bolotnyy and G. Robins, “Physically unclonable function-based security and privacy in RFID systems,” Pervasive Computing and Communications, 2007. PERCOM, 2007, IEEE International Conference on, pp. 211-220, Mar., 2007.DOI
5 
J. Guajardo, et al, “FPGA Intrinsic PUFs and Their Use for IP Protection,” Cryptographic Hardware and Embedded Systems, 2007. CHES, 2007, Lecture Notes in Computer Science, pp. 63-80, 2007.DOI
6 
G. Suh and S. Devadas, “Physical Unclonable Functions for Device Authentication and Secret Key Generation,” Design Automation Conference, 2007. DAC, 2007, Proceedings of, pp. 9-14, Jun., 2007.DOI
7 
F. Koushanfar and M. Potkonjak, “CAD-based Security, Cryptography, and Digital Rights Management,” Design Automation Conference, 2007. DAC, 2007, Proceedings of, pp. 268-269, Jun., 2007.DOI
8 
J. Lee, et al, “A 20F2/Bit Current-Integration-Based Differential nand-Structured PUF for Stable and V/T Variation-Tolerant Low-Cost IoT Security,” Solid-State Circuits, IEEE Journal of, Vol. 57, No. 10, pp. 2957-2968, Oct., 2022.DOI
9 
J. Park, B. Kim, and J. Sim, “A BER-Suppressed PUF With an Amplification of Process Mismatch Effect in an Oscillator Collapse Topology,” Solid-State Circuits, IEEE Journal of, Vol. 57, No. 7, pp. 2208-2219, Jul., 2022.DOI
10 
L. Lu, T. Yoo, and T. Kim, “A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices,” Circuits and Systems I: Regular Papers, IEEE Transactions on, Vol. 69, No. 6, pp. 2542-2552, Jun., 2022.DOI
11 
D. Jeon, et al, “A 325 F2 Physical Unclonable Function Based on Contact Failure Probability with Bit Error Rate < 0.43 ppm After Preselection With 0.0177% Discard Ratio,” Solid-State Circuits, IEEE Journal of, Vol. 57, No. 7, pp. 1-12, Jul., 2022.DOI
12 
Q. Zhao, et al, “A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise,” Circuits and Systems I: Regular Papers, IEEE Transactions on, Vol. 67, No. 11, pp. 3866-3879, Nov., 2020.DOI
13 
Y. Choi, et al, “Physically unclonable function in 28nm fdsoi technology achieving high reliability for aec-q 100 grade 1 and iso 26262 asil-b,” Solid-State Circuits Conference, 2020. IEEE International, ISSCC, 2020. Feb., 2020.DOI
14 
D. Li and K. Yang, “A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization,” Solid-State Circuits, IEEE Journal of, Vol. 55, No. 1, pp. 98-107, Jan., 2020.DOI
15 
D. Nedospasov and C. Helfmeier, “Invasive PUF Analysis,” Workshop on Fault Diagnosis and Tolerance in Cryptography, 2013, Aug., 2013.DOI
16 
J. Zhang, et al, “A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-per-Device Licensing,” Information Forensics and Security, IEEE Trans. on, vol. 14, no. 8, pp. 1137-1150, Jun., 2016.DOI
17 
J. Delvaux, “Machine-Learning Attacks on PolyPUFs, OB-PUFs, RPUFs, LHS-PUFs, and PUF–FSMs,” IEEE Trans. Inf. Forensic Secur., vol. 14, no. 8, pp. 2043-2058, Aug. 2019.DOI
18 
W. Z. Yu and Y. M. Wen, “Efficient hybrid side-channel/machine learning attack on XOR PUFs,” Electronics Letters, vol. 55, no. 20, pp. 1080-1082, Oct. 2019.DOI
19 
U. Rührmair, et al, “PUF modeling attacks on simulated and silicon data,” Information Forensics and Security, IEEE Transaction on, vol. 8, pp. 1876-1891, Nov., 2013.DOI
20 
M. Majzoobi, F. Koushanfar, and M. Potkonjak, “Lightweight secure PUFs,” Computer-Aided Design, 2008. ICCAD, 2008, IEEE/ACM International Conference on, pp. 670-673, Nov., 2008.DOI
21 
D. Lim, et al, “Extracting secret keys from integrated circuits,” Very Large Scale Integration (VLSI) Systems IEEE Transactions on, vol. 13, pp. 1200-1205, Oct., 2005.DOI
22 
Q. Chen, et al, “The Bistable Ring PUF: A new architecture for strong Physical Unclonable Functions,” Hardware-Oriented Security and Trust, 2011. HOST, 2011, IEEE International Symposium on, pp. 134-141, Jun., 2011.DOI
23 
J. Guajardo, et al, “Physical Unclonable Functions and Public-Key Crypto for FPGA IP Protection,” FPGA, 2007, Field Programmable Logic and Applications, International Conf. on, Aug., 2007.DOI
24 
S. Kumar, et al, “The butterfly PUF: protecting IP on every FPGA,” Hardware-Oriented Security and Trust, 2008. HOST, 2008, IEEE International Symposium on, pp. 67-70, Jun., 2008.DOI
25 
R. Maes, P. Tuyls, I. Verbauwhede, “Intrinsic PUFs from flip-flops on reconfigurable devices,” Information and System Security, 2008. WISSec, 2008, Benelux Workshop on, pp. 1-17, 2008.URL
26 
R. Maes and I. Verbauwhede, “PUF: a study on the state of the art and future research directions,” Toward Hardware-intrinsic security, springer-Verlag, pp. 3-17, 2010.URL
27 
M. Majzoobi, F. Koushanfar, and M. Potkonjak, “Testing techniques for hardware security,” ITC, 2008, IEEE International Test Conference, pp. 1-10, Oct. 2008.DOI
28 
A. Maiti, et al, “A Large Scale Characterization of RO-PUF,” Hardware-Oriented Security and Trust, 2010. HOST, 2010, IEEE International Symposium on, pp. 94-99, Jun., 2010.DOI
29 
C. Chang and C. Lin, “LIBSVM: A library for support vector machines,” Intelligent Systems and Technology, ACM Transactions on, Vol. 21, No. 3, pp. 1-27, Apr., 2011.DOI