I. INTRODUCTION

The damage caused by an electrostatic discharge (ESD) in an integrated circuit (IC) has become a more serious problem as advances in semiconductor process technology have led to the continuing miniaturization of IC. The increase in demand for high voltage analog and smart power IC technology requires for improvement in the design of ESD protection circuit ^(1,2). Such ICs can be used for a variety of applications, including for power management, display driver, and automotive applications. As a result, it is necessary to design a reliable ESD protection circuit.

In the smart poser technology, MOSFET and silicon controlled rectifier (SCR) are commonly used as an on-chip ESD protection circuit. MOSFET is not suitable for ESD protection due to their low robustness and large size. On the other hand, SCR can drive a high current and provide robust protection against ESD because a discharge path is formed inside the silicon substrate. However, it has a low holding voltage of about 2 V, which is the turn-on voltage of the parasitic NPN/PNP bipolar transistor. The ESD protection circuit may be triggered by unwanted noise and overshoot voltage, causing a latch-up problem during normal operation due to its low holding voltage. A latch-up results in a malfunction during normal operation and causes destruction of the IC due to the presence of a high current ⁽³⁾.

In this paper, a novel SCR-based ESD protection circuit is proposed for 5 V supply voltage application which has low trigger voltage and high holding voltage compared with conventional SCR. The proposed ESD protection circuit was fabricated by 0.18 µm BCD process and verified electrical characteristics through the measurement of TLP ⁽⁶⁾.

II. PROPOSED SCR BASED ESD PROTECTION CIRCUIT

Structural features of the proposed ESD protection circuit are as follows. N + diffusion region of the junction between the left N-well and P-well is made to be the role of the drain of Grounded-Gate N-Channel MOS (GGNMOS), N + diffusion region to the source role of the GGNMOS and the Gate that has been inserted into the P-well, and P+ drift region as P-body connected to the cathode to form a GGNMOS operation. So, parasitic NPN bipolar transistor Q1 is further operative. Fig. 1 shows the cross-section of the proposed ESD protection circuit and conventional ESD protection circuit. And Fig. 2 shows the equivalent circuit of the proposed ESD protection circuit.

Fig. 1. (a) Cross-section of the conventional ESD protection circuit, (b) Cross-section of the proposed ESD protection circuit.

Fig. 2. (a) The equivalent circuit of the proposed ESD protection circuit.

The behavior of the proposed ESD protection circuit is as follows. When ESD surge is applied to anode, junction between N+ diffusion and P-well is reverse biased until it goes into avalanche breakdown. Electron-Hole Pair (EHP) is created by avalanche breakdown. The current of created Holes moves to P-well area and increase potential of P-well. When the potential between the P-well and N+ cathode of GGNMOS reaches about 0.7 V, the junction is forward-biased and parasitic NPN bipolar transistor (Q1) turn on. Then, parasitic PNP bipolar transistor (Q2) of SCR is turned on. When the current of PNP bipolar transistor (Q2) flow to P-well, its current generates a voltage drop a cross P-well and turns on the parasitic NPN bipolar transistor (Q3). At this point, parasitic PNP bipolar transistor and NPN bipolar transistor discharge ESD currents as positive feedback through the Cathode. In order to analyze the holding voltage of the proposed ESD protection circuit, the design parameter D1, D2 were set. D1 is the length of Gate of GGNMOS, it is control P-well length, which means the base region of the parasitic NPN bipolar transistor. D2 is the length of the N+ floating region and is related to the holding voltage.

III. EXPERIMENTAL RESULT

1. TLP and Leakage Measurement

Transmission Line Pulse (TLP) measurement method is most widely used method to analyze electrical characteristics and robustness characteristics for ESD protection circuit. The TLP produces a rectangular pulse with a rising time of 10 ns and a pulse width of 100 ns ⁽⁴⁾. In this paper, HBM and MM tests were conducted according to ESD standard ⁽⁹⁾. The proposed ESD protection circuit was fabricated by using a 0.18 µm BCD process.

The trigger voltage (VT) is the voltage at which the ESD protector turns ON. The trigger voltage should be less than the voltage at which the generic elements used in the internal circuit break down and the gate oxide breakdown voltage. The holding voltage (VH) is the minimum voltage across the device during ESD current discharge when it is turned on after the ESD protector is triggered.

The holding voltage must be greater than the operating voltage of the internal circuit. The secondary trigger voltage and trigger current refer to the current and voltage at the time the ESD protector is destroyed. It is known that the secondary trigger current is mainly used as an index of the ESD protection device's durability characteristics, and the value can be converted into HBM, MM, and the like.

Fig. 3 shows the TLP I-V curve of the conventional SCR and Proposed ESD protection circuit. The trigger voltage of the proposed ESD protection circuit is 10.58 V and it has a lower voltage than 11 V for the SCR. The reason for the low trigger voltage is that avalanche breakdown occurs at N+ bridge/P-well junction as N+ bridge is high doping. As holding voltage is 3.98 V, it is higher than the conventional SCR.

Fig. 3. (a) Fabricated chips, (b) TLP I-V curve of conventional SCR and the proposed ESD protection circuit.

Design parameter D1 is Gate length of GGNMOS. The gate length is the base region parasitic NPN bipolar transistor (Q1, Q3), and controls P-well length. As the gate length increase, the base width of the NPN bipolar transistor increases. As the base width increase, the current gain of the NPN bipolar transistor decreases because the emitter injection efficiency decrease. So, the holding voltage increases and was measured at 3.41 V, 3.93 V, 4.36 V, and 5.65 V for D1 values of 1 µm, 2 µm, 3 µm and 4 µm. Fig. 4(a) shows the TLP I-V curve as D1 varies. And second design parameter D2 is that N+ floating diffusion region inserted in the N-well. The more the design variable D2 increases, the holding voltage increased up to 4.21 V 6.09 V, and 7.24 V, respectively, as current gain decreases with the increases in the PNP bipolar base width. Table 1 shows the results of the measurements for holding voltage and second breakdown current.

Fig. 4. Measured design parameter TLP I-V characteristics (a) D1, (b) D2.

Table 1. TLP characteristics of the proposed ESD protection circuit resulting from the D1, D2 design parameters

Design Parameter	Electrical Characteristics
	VT[V]	VH[V]	IT2[V]
Conventional SCR	21.88	3.6	6.3
Optimized Circuit	10.11	7.24	5.36
D1 [µm]	VT[V]	VH[V]	IT2[V]
1	9.53	3.41	6.89
2	10.29	3.93	6.8
3	10.44	4.36	6.88
4	10.39	5.65	6.95
D2 [µm]	VT[V]	VH[V]	IT2[V]
0	9.53	3.41	6.89
3	9.4	4.21	5.61
6	9.4	6.09	5.52
9	9.4	7.24	5.36

IV. CONCLUSION

In this paper, a new SCR-based structural ESD protection circuit is proposed with low trigger voltage and high robustness characteristic for a 5 V application. The proposed structure is developed to reduce the avalanche breakdown voltage of the Conventional SCR. Also, due to the parasitic NPN bipolar transistor operates within GGNMOS discharge path the ESD current through the three parasitic transistors. Moreover, the results corresponding to each of the design variables verified the performance of the proposed circuit. Through TLP measurement, the Trigger voltage of the measurement result of the fabricated chips in the proposed device is 10.58 V, the holding voltage is 7.24 V. Thus, the proposed ESD protection circuit has a low trigger voltage and a high holding voltage characteristic having latch-up immunity. And the reliability of the low voltage application integrated circuits.