Lin Jin-Fa1
Yu Shao-Wei1
Tsai Chang-Ming1
Sheu Ming-Hwa1
-
(Information and Communication Engineering, Chaoyang University of Technology)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Low power, low voltage, flip-flop
I. INTRODUCTION
Low-power design is progressing because of the growing interest in high energy-constrained
mobile applications, such as wearable devices and the internet of things. In the applications,
operating speed is no longer the main concern issue. Instead, power is the main issue
of the design aspects. Digital designs often employ extensive FF for data buffering
or pipelining, and the circuit efficiency of FF designs largely affects the overall
area and power consumption. New FF designs evolve constantly with the advances of
new process technology as well as the target applications [1-4]. In this paper, we revisit the basic FF problem. A transmission gate based FF (TGFF)
as shown in Fig. 1(a), is the most widely used one. One possible drawback of this design is the excessive
work load to the clock signal which leads to larger dynamic power even when the data
switching activity is lower. Recently, true-single-phase clock operation FFs are presented
targeting low power applications [5-8]. The major idea is to reduce clock signal loading via circuit reduction. In this
paper, we present a novel SR-latch based FF design. It also features a true-single-phase
clock operation, which greatly alleviates the clock loading. The design also exhibits
better energy consumption when compared with previous FF designs.
II. PROPOSED DESIGN
The FF circuit design idea initiates with a low power SR-latch based FF named ACFF
[5] as shown in Fig. 1(b). In this design, the data contention problem encountered by slave-latch and the advantage
of power saving diminishes as the rise of the switching activity. The p-MOS type pass-transistor
logic based master latch also causes a longer setup time performance especially operates
at lower voltage. Moreover, this design suffers from a power leaking problem (floating)
when certain input and internal node combinations occur [7].
In view of these possible drawbacks, an enhanced design applying to the Set-Reset
latch based design is developed as shown in Fig. 2. For pull-down network (n1 and n2), one CK controlled nMOS transistor can be shared
by the two discharging paths. For pull-up network (p1 and p2), nodes x2 and x2-bar
are always complementary to each other, implying that either the x3 or x4 controlled
pMOS transistor will turn on as indicated in the small figure in Fig. 2(b). The drain node of the turned on pMOS transistor corresponds to a virtual $V_{DD}$.
Thus a clock-driven transistor can be removed without affecting the function with
fully static operation. The resultant circuit design is shown in Fig. 2 (b).The transistor-count is reduced to 24 and only 2 transistors (1pMOS and 1nMOS)
are driven directly by the clock signal. All these factors contribute to a significant
power consumption and energy saving of the design [5]. Moreover, the height of nMOS transistors of proposed design in series is only 2
while design [6-7] are pMOS transistors in series is 3-transistor, smaller sized transistors can thus
be adopted to achieve the FF design. The speed performance, power consumption, and
layout area are all better than previous designs. Simulation waveforms depict the
details of each node within our design, as shown in Fig. 3(a). All internal nodes assume a full voltage swing.
We also noticed a potential internal node floating problem associated with ACFF design.
When the clock signal was frozen at logic 1 and the input data changed, both internal
nodes $X$ and $XB$ were determined to be in a floating state shown in Fig. 3(b).This means the design may suffer from the static power problem when the FF design
is clock gated. Post-layout simulation results also show that, the power consumption
of ACFF is over 3.5 times that of our design in this particular case i.e. 1MHz/0.5V,
which should not be overlooked when the ACFF is employed in the low power designs.
Fig. 1. Conventional FF designs. (a) TGFF. (b)ACFF[1].
Fig. 2. Proposed footless flip-flop design. (a) Logic schematic. (b) MOS schematic
and virtual $V_{DD}$ circuit scheme.
Fig. 3. Post-layout simulation waveforms. (a)Proposed FF design. (b)ACFF design (floating
problem).
Fig. 4. . FFs performances. (a)Average power consumption at different data switching
activity. (b)$PDP_{CQ}$ performances at different process corners (@12.5% switching
activity).
Fig. 5. Timing evaluation results. (a)Setup time. (b)Hold Time.
Table 1. Comparison of FF design @TT-Corner
III. SIMULATION RESULTS
Four FF designs, i.e., the TGFF, ACFF, sense- amplifier FF (SAFF) [9] and our design are compared. The target technologies are the TSMC 180nm CMOS process.
Transistor sizing is subject to the optimization of power-delay-product ($PDP_{CQ}$)
with the same high on layout schematic. The operating conditions are set as 1MHz/0.5V
to emphasize the low voltage and low power applications. Five test patterns, each
corresponding to a different data switching probability are applied.
The simulation results are summarized in Table 1. In terms of the power consumption behavior, our design is the most power efficient.
The power consumption (at 25% switching) of the proposed design is 68.7% less than
TGFF. In terms of the setup time performance, ACFF plays higher than TGFF design due
to weak pMOS type pass transistor logic. The setup time of our design is 63.7% smaller
compared to ACFF design. As for the hold time, the all designs are showing a negative
number expect the SAFF. Our design also leads in $PDP_{CQ}$. When the switching activity
is 25%, the PDP saving against the TGFF, SAFF and ACFF can reach 68.7%, 35.8% and
52.4%, respectively.
Fig. 4 shows the average power at different data switching activity and $PDP_{CQ}$ performance
of these FF designs at different process corners. All designs function properly subject
to process variations expect the ACFF design failed at SF corner. Note that, for each
process corner, the setup time and hold time were scanned to obtain the best PDP number
as shown in Fig. 5. All FF designs were determined to function properly under process variations. Our
design maintained its lead in most of cases. Therefore, this evaluation also verifies
the performance consistency of the proposed design.
VI. CONCLUSIONS
A novel Set-Reset latch based FF supporting low voltage and low power operations is
presented. Our design is successfully removed 2-transistor controlled by clock signal
to achieve power and energy performance. Conducted evaluations show that our design
is the most power economical in all compared designs.
ACKNOWLEDGMENTS
This work was supported by the Ministry of Science and Technology, Taiwan under contract
No. 107-2221-E- 324-017-MY2 and the grants form of Taichung Veterans General Hospital
and Chaoyang University of Technology (TCVGH-CYUT1088803) Taichung, Taiwan. The authors
would like to thank National Chip Implementation Center (CIC), Taiwan for technical
support in simulations.
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