Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2019-10 (Vol.19 No.05)
  4. 10.5573/JSTS.2019.19.5.505
XML PDF INFO REF

REFERENCES

1 
Kawaguchi H., Sakurai T., May. 1998, A reduced clock-swing flip-flop(RCSFF) for 63% power reduction, IEEE J. Solid-State Circuits, Vol. 33, No. 5, pp. 807-811DOI
2 
Stojanovic V., Oklobdzija V., Apr. 1999, Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems, IEEE J. Solid-State Circuits, Vol. 34, No. 4, pp. 536-548DOI
3 
Kong B., Kim S., Yun Y., Aug. 2001, Conditional-capture flip-flop for statistical power reduction, IEEE J. Solid-State Circuits, Vol. 36, No. 8, pp. 1263-1271DOI
4 
Consoli E., Alioto M., Palumbo G., Rabaey J., Conditional push-pull pulsed latch with 726 fj.ps energy delay product in 65nm CMOS, in Proc. IEEE Dig. ISSCC, 2012, pp. 482-483Google Search
5 
Chen K., al et, Feb. 2011, A 77% energy saving 22-transistor single phase clocking D-flip-flop with adoptive-coupling configuration in 40nm CMOS, ISSCC Dig. Tech. Papers, pp. 338-339DOI
6 
Kawai N., al et, Nov. 2014, A fully static topologically-compressed 21- transistor flip-flop with 75% power saving, IEEE J. Solid-State Circuits, Vol. 49, No. 11, pp. 2526-2533DOI
7 
Lin J.-F., al et, Nov. 2017, Low-power 19-transistor true single-phase clocking flip-flop design based on logic structure reduction schemes, IEEE Trans. Very Large Scale Integr.(VLSI) Syst, Vol. 25, pp. 3033-3044DOI
8 
Stas F., Bol D., Mar. 2018, A 0.4-V 0.66-fJ/cycle retentive true-single-phaseclock 18T flip-flop in 28-nm fully-depleted SOI CMOS, IEEE Trans. Circuits Syst. I, Reg, Papers, Vol. 65, No. 3, pp. 935-945DOI
9 
Nikolic B. N., Oklobdzija V. G., Stojanovic V., al et, Jun. 2000, Improved sense-amplifier-based flip-flop: design and measurements, IEEE J. Solid-State Circuits, Vol. 35, No. 6, pp. 876-884DOI