Dai Liang1
Lü Weifeng1*
Lin Mi1
-
(Hangzhou Dianzi University, Hangzhou, China)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Dual-metal gate, nanowire transistor, process variation, work-function variation (WFV)
I. INTRODUCTION
Owing to its strong control capability over a channel, a metal-oxide-semiconductor
field-effect transistor (MOSFET) with multiple gate structures is advantageous for
alleviating technical problems posed by aggressive down scaling of the device dimensions,
such as short-channel effects (SCEs) (1-5). This advantage is attributed to the solution form of the drain electrical potential
from Poisson’s equation, where λ is defined as the natural length. A small λ implies
that the drain electrical potential decreases rapidly such that the impact of the
drain on the channel will be suppressed, which will enable the gate to control the
switching of the device (3,6-8). Compared to other multiple gate structures, the gate-all-around (GAA) nanowire metal-oxide-semiconductor
field-effect transistor (NWFET) has the smallest natural length in the same technology
node; hence, it has excellent gate control capability for alleviating SCEs (6). Therefore, according to the International Technology Roadmap for Semiconductors,
high-performance integrated circuits are witnessing development in the direction of
GAA NWFETs (9).
A suitable dual-metal gate (DMG) structure can effectively improve the device performance.
Selecting a low work function (WF) metal near the drain adjusts the channel potential
and electric field distributions to suppress the drain-induced barrier, thereby improving
the carrier transport efficiency in DMG devices (10-12). Process variations such as random discrete doping, line-edge roughness and work-function
variation (WFV) have been recognized as primary causes in advanced MOSFETs. At present,
the commonly used high-k/metal gate technique induces metal WFV, which has been reported
as a major random source that adversely affects the device performance, which is further
degraded with the scaling of the device dimensions (3,13-17).This is because the WF of the gate metal depends on its grain orientation, which
is extremely difficult to control during fabrication by existing technologies. Although
the impact of WFV on a single metal gate (SMG) structure has been reported from different
aspects, the WFV-induced variability in DMG structures remains to be addressed. In
addition, compared with the conventional inversion-mode (IM) transistor, junctionless
(JL) devices show considerable potential for future technology nodes owing to their
stronger immunity to SCEs, simpler fabrication process, lower electric field in the
“on”- state, etc. (11,15,16,18-20). Thus, we investigate and compare the effects of WFV- induced performance variability
in IM and JL DMG GAA NWFETs.
II. DEVICE STRUCTURE AND SIMULATION
Fig. 1. (a) WFV and structure of JL and IM DMG GAA NWFETs, (b) Cross section along
the x-axis at x = 0. M1 is the control gate and M2 is the screen gate.
Fig. 1 shows a schematic of the JL or IM DMG GAA NWFETs used in this study. The JL and IM
DMG GAA NWFETs have the same size, and the device dimensions are summarized in Table 1. DMG devices have two different gate metals (M1 and M2). In this study, TiN and TaN
are used as M1 and M2, respectively. The physical properties of TiN and TaN are summarized
in Table 2 (13,14), where ‘Probability’ refers to the possibility of the occurrence of grains with different
orientations. It is worth noting that TiN can be used alone as the metal gate in an
SMG n-channel device (i.e., L1/L = 1), whereas TaN (i.e., L1/L = 0)
cannot be used alone.
Table 1. DMG IM and JL GAA NWFET Parameters
Parameter
|
IM
|
JL
|
Radius (nm)
|
4
|
4
|
Gate Length (nm)
|
20
|
20
|
Oxide thickness (nm)
|
2
|
2
|
Channel Doping (cm−3)
|
acceptor 1×1016
|
donor 1×1019
|
Source Doping (cm−3)
|
donor 1×1019
|
donor 1×1019
|
Drain Doping (cm−3)
|
donor 1×1019
|
donor 1×1019
|
Table 2. TiN and TaN Physical Properties
Metal
|
Orientation
|
WF (eV)
|
Probability
|
TiN
|
<100>
|
4.6
|
60%
|
<111>
|
4.4
|
40%
|
TaN
|
<100>
|
4.0
|
50%
|
<200>
|
4.15
|
30%
|
<220>
|
4.8
|
20%
|
In addition, we explore the effects of the ratio of L1 to L on the performance
variability caused by WFV by setting L1/L to 0, 0.2, 0.4, 0.6, 0.8, and 1 for
the JL and IM DMG GAA NWFETs. All the simulations are carried out using a dedicated
randomization algorithm provided in Sentaurus. In the simulation, the models selected
or activated include the drift-diffusion model in combination with the density gradient
for quantum corrections; the mobility model that incorporates the high-field saturation,
doping dependence, and field perpendicular to the semiconductor–insulator interface;
the Shockley Read Hall (SRH) model for recombination generation; and the evaluation
of the SRH lifetimes according to the Scharfetter model. To observe the effects of
WFV, 200 samples are randomly generated for each of the above-mentioned cases, and
the average metal grain size is set to 5 nm (21).
III. RESULTS AND DISCUSSION
In Fig. 2, it can be seen that WFV causes dispersion of the drain current as the gate-source
voltage (VGS) is swept from 0 to 1 V at a drain voltage (VDS) of 1 V. As
shown by the dispersion of the transfer curve for the simulated devices with L1/L
varying from 0 to 1 in steps of 0.2 in these figures, WFV can cause electrostatic
integrity variability in both IM and JL DMG GAA NWFETs. As the L1/L decreases,
the area occupied by the discrete curve is found to increase gradually, which implies
that the WFV-induced performance variability in both IM and JL DMG GAA NWFETs becomes
more severe. In particular, when L1/L is less than 0.4, the dispersion of the
drain current increases sharply. Moreover, it can be seen that as L1/L decreases,
the current in the “off” state increases significantly. This increase occurs because
the threshold voltage (VTH) decreases with L1/L (8,22).
Fig. 2. Dispersions caused by WFV of drain current vs. gate voltage (VGS) for
IM and JL DMG GAA NWFETs.
To better analyze the experimental results, the WFV-induced variation of VTH,
transconductance (gm), saturation current (Isat), and subthreshold slope
(SS) are determined for each case in terms of their average and standard deviation,
and these parameters are plotted in Fig. 3-6. Note that VTH is extracted using the constant-current method, where the fixed
current is set to 0.1 μA/μm. Isat is based on the maximum current value in the
Id-Vg curve. gm is the maximum transconductance of the given Id-Vg
curve. In addition, SS is extracted by SS = d Vgs/d(log10Id). Because TaN alone is not suitable as a metal gate, SS and VTH for the
devices are absent when L1/L = 0. As shown in Fig. 3, the average VTH decreases with L1/L, especially when L1/L is
less than 0.4. Further, when L1/L lies between 0.6 and 1, the relative deviations
of VTH for both JL and IM GAA NWFETs do not change significantly.
Fig. 3. Average and relative deviation of VTH variations caused by WFV at different
values of L1/L.
However, the fluctuation in the WFV-induced VTH increases sharply when L1/L
is less than 0.4. Moreover, it can be seen from Fig. 3 that the relative deviations of VTH for the IM device are smaller than those
for the JL device. In other words, the IM DMG GAA NWFET has stronger immunity to the
VTH variation caused by WFV compared to its JL counterpart of the same size at
different L1/L. This difference in immunity can be attributed to the larger
effective gate area of the IM device (19). In addition, it can be observed that the average VTH of the JL GAA NWFET is
lower than that of the IM GAA NWFET. Thus, it can be concluded that the JL GAA NWFET
and the IM GAA NWFET have different conduction mechanisms: an inversion layer is formed
when the IM GAA NWFET is turned on (23). Meanwhile, when L1/L is decreased from 1 to 0.6, the variability of VTH
is small, but the average VTH of the JL and IM DMG GAA NWFETs decreases by approximately
0.15 V. Thus, it is verified that the DMG can be used to adjust VTH.
Fig. 4. Average and relative deviation of Isat variations caused by WFV at different
values of L1/L.
Fig. 5. Average and relative deviation of SS variations caused by WFV at different
values of L1/L.
From Fig. 4, it can be seen that the relative deviation of Isat of the IM device is larger
than that of the JL device. This is because, in the “on” state, the conducting current
is concentrated at the channel center (called the body current effect) for a JL device
and on the channel surface for an IM device. Thus, the interface scattering effects
of the JL are smaller than those of the IM device (3,8,19). Therefore, the variability of Isat is more severe in the IM device.The SS characteristics
of the IM and JL DMG GAA NWFETs as L1/L is varied from 0 to 1 in steps of 0.2
are shown in Fig. 5. Compared with the corresponding SMG GAA NWFET that employs TiN, the DMG GAA NWFET
has a larger SS.This is mainly because SS is inversely proportional to the effective
length (11,24), and the effective length of the IM and JL DMG GAA NWFETs is only slightly greater
than L1 in the subthreshold region (11). By contrast, the effective length of the SMG GAA NWFET is slightly greater than
L. As L1 or L1/L decreases, the effective length decreases; therefore,
the SS of the DMG GAA NWFET increases gradually (11,22). The average and relative deviation of SS are both not large when L1/L lies
between 0.4 and 1; however, when L1/L is less than 0.4, both increase sharply
for the IM and JL DMG GAA NWFETs.
Fig. 6. Average and relative deviation of gm variations caused z.
Fig. 6 shows the characteristics of gm for the JL and IM DMG GAA NWFETs with different
L1/L. Note that gm remains basically unchanged when L1/L is varied
from 0.6 to 1. By contrast, the relative deviation of gm decreases when L1/L
is varied 1 to 0.6 in steps of 0.2. However, the fluctuation of gm increases
sharply as L1/L decreases below 0.4.
Fig. 7. WFV causes changes in the correlation between SS and VTH for the devices.
Scatter plots of (a)-(e) SS vs. VTH and (f)-(j) gm vs. Isat obtained
by varying L1/L from 0 to 1 in steps of 0.2. IM corresponds to the lower x-axis
and the left y-axis, and JL corresponds to the upper x-axis and the right y-axis.
Fig. 7(a)-(e), shows the scatter plots of SS and VTH, which indicate good agreement between
the JL and IM DMG GAA NWFETs at different L1/L. In addition, the scatter plots
of gm and Isat are shown in Fig. 7(f)-(j). The correlation coefficients (ρ) of the JL and IM GAA NWFETs are calculated according
to Eq. (1). When L1/L is greater than 0.2, the correlation coefficient between SS and
VTH is small; by contrast, when L1/L is reduced to 0.2, it increases.
This occurs because the effective length of the IM and JL DMG GAA NWFETs is only slightly
greater than L1 in the subthreshold region (11). Moreover, the changes in the correlation between SS and VTH of the JL and IM
DMG GAA NWFETs are similar to the changing trend of L1/L. However, it is interesting
that we found from Fig. 7(f)-(j) that the correlation between gm and Isat is not obvious with the changing
trend of L1/L compared with that of SS and VTH.
Fig. 8. Electric field (MV*cm−1) in DMG IM and JL GAA NWFETs at L1/L
= 0.6 near the source (a, c) and drain (b, d).
Fig. 8 shows the electric field distribution of the DMG IM and JL GAA NWFETs at L1/L
= 0.6 near the source and drain. It can be observed that the strength of the electric
field in the channel near the drain is relatively high. Thus, the electric field distribution
in the channel near the drain is not uniform. Therefore, the region near the drain
is expected to experience more severe fluctuation in the electrostatic potential compared
to the region near the source (25).
For gm, VTH, and SS, when L1/L is less than 0.4, their relative deviations
increase sharply. Moreover, changes in L1/L do not have a significant effect
on the Isat of the device. Thus, it is necessary to weight the value of L1/L
for a DMG device. Some studies have considered it suitable to set L1/L = 0.5
when the effect of WFV is ignored (11). However, we find that L1/L should be slightly greater than 0.5 when the effect
of WFV is considered.
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Author
Liang Dai received the bachelor's
degree in Electronics engineering
from Yuncheng University in 2013.
He is currently working toward the
master degree with the Key Laboratory
for RF Circuits and Systems,
Hangzhou Dianzi University, Hangzhou,
China.
Weifeng, Lü received the B.S.
degree in information engineering in
2001, and M.S. and Ph. D. degrees in
electronic science and technology
from Zhejiang University, in 2004
and 2011, respectively.
He joined the
School of Electronics and Information,
Hangzhou Dianzi University, Hangzhou, China
in 2004 as a Lecture from 2005 to 2014 and as an
associate Prof. from 2016.
He is a visiting scholar at The
University of Texas at Austin.
Austin, TX, USA. His
research interests mainly include design for
manufacturing, statistical modeling of process variations,
and nanometer CMOS devices.
Mi Lin received the Bachelor’s
degree in Electronic Engineering
from Zhejiang University, Hangzhou,
in 2001, and M.S and the Ph.D
degrees in circuit and system from
Zhejiang University, Hangzhou,
Zhejiang, China, in 2010.
She joined
the School of Electronics and Information, Hangzhou
Dianzi University, Hangzhou, Zhejiang Province, China
in 2004 as a Lecture from 2005 to 2014 and as an
associate Prof. from 2015.
Her current research interests
in resonant tunneling devices, NDR circuits and related
digital circuits and multiple-valued logic technologies.