Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2020-08 (Vol.20 No.04)
  4. 10.5573/JSTS.2020.20.4.349
XML PDF INFO REF

REFERENCES

1 
Pradhan K.P., Saha S.K., Sahu P.K., 2017, Impact of Fin Height and Fin Angle Variation on the Performance Matrix of Hybrid FinFETs, IEEE Trans. Electr. Dev, Vol. 64, pp. 52-57DOI
2 
Nagy D., Indalecio G., García-Loureiro A.J., 2017, Metal grain granularity study on a gate-all-around nanowire FET, IEEE Trans. Electr. Dev, Vol. 64, pp. 5263-5269DOI
3 
Lü W.F., Dai L., 2019, Impact of work-function variation on analog figures-of-merits for high-k/metal-gate junctionless FinFET and gate-all-around nanowire MOSFET, Microelectron. J., Vol. 84, pp. 54-58DOI
4 
Hisamoto D., Lee W.C., Kedzierski J., 2000, FinFET-a self-aligned double-gate MOSFET scalable to 20 nm, IEEE Trans. Electr. Dev., Vol. 47, pp. 2320-2325DOI
5 
Narendar V., Mishra R.A., 2015, Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs), Superlattices. Microstruct., Vol. 85, pp. 357-369DOI
6 
Colinge J.P., 2004, Multiple-gate SOI MOSFETs, Solid. State. Electron., Vol. 48, pp. 897-905DOI
7 
Colinge J.P., 2008, FinFETs and Other Multi-Gate Transistors, Springer Science+Business Media LLCGoogle Search
8 
Wu Y.C., Jhan Y.R., 2018, 3D TCAD Simulation for CMOS Nanoeletronic Devices, Springer Nature Singapore Pte LtdGoogle Search
9 
Nayak K., Bajaj M., Konar A., 2014, CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET, IEEE Trans. Electr. Dev., Vol. 61, pp. 3066-3074DOI
10 
Long W., Ou H., Kuo J.M., 1999, Dual material gate (DMG) field effect transistor, IEEE Trans. Electr. Dev., Vol. 46, pp. 865-870DOI
11 
Lou H., Zhang L., Zhu Y., 2012, A Junctionless Nanowire Transistor with a Dual-Material Gate, IEEE Trans. Electr. Dev., Vol. 59, pp. 1829-1836DOI
12 
Gupta S.K., Kumar S., 2018, Analytical Modeling of a Triple Material Double Gate TFET with Hetero-Dielectric Gate Stack, Silicon, Vol. 11, pp. 1355-1369DOI
13 
Dadgour H.F., Endo K., De V.K., 2010, Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors-Part I: Modeling, Analysis, and Experimental Validation, IEEE Trans. Electr. Dev., Vol. 57, pp. 2504-2514DOI
14 
Dadgour H.F., Endo K., De V.K., 2010, Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors-Part II: Implications for Process, Device, and Circuit Design, IEEE Trans. Electr. Dev., Vol. 57, pp. 2515-2525DOI
15 
Jiwon K., Hyeongwan O., Bo J., 2018, Analog Figure-of-Merits Comparison of Gate Workfunction Variability and Random Discrete Dopant Between Inversion-Mode and Junctionless Nanowire FETs, J. Nanosci. Nanotechnol., Vol. 18, pp. 6598-6601DOI
16 
Nawaz S.M., Mallik A., 2016, Effects of Device Scaling on the Performance of Junctionless FinFETs Due to Gate-Metal Work Function Variability and Random Dopant Fluctuations, IEEE Electr. Dev. Lett., Vol. 37, pp. 958-961DOI
17 
Indalecio G., García-Loureiro A.J., Iglesias N. S., 2016, Study of Metal-Gate Work-Function Variation Using Voronoi Cells: Comparison of Rayleigh and Gamma Distributions, IEEE Trans. Electr. Dev., Vol. 63, pp. 2625-2628DOI
18 
Lee C.W., Afzalian A., DAkhavan N., 2009, Junctionless multigate field-effect transistor, Appl. Phys. Lett., Vol. 94, pp. 053511DOI
19 
Nawaz S.M., Dutta S., Chattopadhyay A., 2014, Comparison of Random Dopant and Gate-Metal Workfunction Variability Between Junctionless and Conventional FinFETs, IEEE Electr. Dev. Lett., Vol. 35, pp. 663-665DOI
20 
Lee C.W., Ferain I., Afzalian A., 2010, Performances estimation of junctionless multigate transistors, Solid. State. Electron., Vol. 54, pp. 97-103DOI
21 
Sentaurus Device User Guide, Synopsys, Inc, Mountain View, CA, USA, 2017Google Search
22 
L.Dai , Lü W.F., 2019, Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs, Electronics, Vol. 8, pp. 282DOI
23 
Liu K.M., Wang W.S., 2017, Effects of the correlation length of line edge roughness on the variability of 14-nm inversion-mode and junctionless FinFETs, Int. J. Electron. Lett., Vol. 6, pp. 220-230DOI
24 
Saxena M., Haldar S., Gupta M., 2004, Design considerations for novel device architecture: hetero-material double-gate (HEM-DG) MOSFET with sub-100 nm gate length, Solid. State. Electron., Vol. 48, pp. 1169-1174DOI
25 
Lee Y., Shin C., 2017, Impact of equivalent oxide thickness on threshold voltage variation induced by work-function variation in multigate devices, IEEE Trans. Electr. Dev., Vol. 64, pp. 2452-2456DOI