I. INTRODUCTION

With increasing functional and performance demands on electronic devices, power noise management has been one of the most critical issue in the development process. In particular, the consumer electronic devices seriously require robust power noise quality in terms of system-level power integrity ^(1-3). In order to improve the power noise quality in the entire system, the complex power integrity issues arising from integrated circuit (IC) design, package paths, printed circuit board (PCB) environments and software operation, should be considered. Since power noise considerations in the IC design stage is typically performed during or after the physical implementation of the placement and routing (P&R), the improvement of the system power noise quality by adjustment of factors associated with off-chip power integrity can be a challengeable task.

For system level power noise problems, many efforts on the early phase of development process have been conducted ^(4-19). However, since the previous methodologies of ^(4-12) require the IC layout information of the physical implementation, power noise management in concurrent system design is not appropriate in terms of the development turnaround time. In addition, the power noise estimation during the design stage of off-chip design ^(13-19) is a backward solution that does not optimize the power noise at the IC level.

In order to estimate the power noise of the system on chip (SoC) from the perspective of the system designer, our previous research of ⁽²⁰⁾ developed a novel simplified chip power model (SCPM). The SCPM, which models of the current profile with local blocks and clocks, enables the overall power noise estimation with the power delivery network (PDN) in the early design stage before SoC physical implementation without the silicon netlist or geometry layout information. However, when applying the collective ratio between the current peak and base current, some specified blocks do not match the power noise spectrum estimation. Due to adoption of the simplified and generalized current profile, the developed methodology can exhibit the low power noise estimation accuracy for specified applications such as display timing controllers (TCONs). In this paper, an enhanced SCPM methodology for TCONs is presented.

Section II reviews our previous SCPM methodology and demonstrates an enhanced SCPM methodology for display TCONs. Section III and IV provide the verification results and conclusions.

II. SCPM METHODOLOGY FOR DISPLAY TIMING CONTROLLERS

This section briefly reviews our previously proposed PDN design process using the SCPM methodology in ⁽²⁰⁾. Subsequently, an enhanced SCPM methodology, which includes the current profile slope information for display TCONs, is proposed.

III. VERIFICATION AND MEASUREMENT RESULTS

We experimentally verified the proposed SCPM methodology with a PDN including the TCON chip, package, and PCB. The PDN for TCON power noise estimation consists of on-chip components (on-die resistor and capacitor), off-chip components (off-chip decoupling capacitors and inductor), and PWL current sources with the current slope information including the external voltage regulator module (VRM) on the PCB as shown in Fig. 3. While the on-chip components are experimentally extracted, the off-chip components are extracted in S-parameter form on the basis of EM simulation. The extracted on-die resistance ROD and capacitance COD values are 2.5 mΩ and 105 nF, respectively. And the package capacitors have 23 mΩ of equivalent series resistance and 1.2 nH of equivalent series inductance. The test vehicle of the display TCON is synchronized with a 300 MHz reference clock and the other peripheral blocks are 933 MHz for the memory controller, while the raw image data receiver block uses a 280 MHz clock. Table 1 shows the current consumption and operating frequency of each TCON block. Unlike the SoC chip in the previous work of ⁽²⁰⁾, each sub-block in the TCON chip of this work operates simultaneously.

The current shape based on the enhanced SCPM methodology with the current profile slope information is modeled as a triangular profile with the accumulated operating TCON blocks. With the exception of the SCPM generation of the LVDS output buffer, all SCPM have a triangular current shape with a transition time of 20% of the clock cycle. Using the current consumption and operating frequency information, the current shapes of each block in the test vehicle are defined according to a 4:1 current peak: static current ratio. Additionally, each is correlated with the current peak and static current after the current transients have been calibrated in the frequency domain. The total current consumption is estimated as 6.48 A based on the root-mean-square (RMS) at the RTL level. As shown in Fig. 4, the estimated transient peak-to-peak noise voltage is 66 mV and 7.18 mV of 300 MHz in the frequency domain.

Fig. 5 shows the evaluation board with the DTV TCON chip for the experimental verification. The test vehicle is assessed in terms of voltage noise while the system runs 3D test movies. To verify the voltage noise simulation results, the bottom point of the thru-via on the center of the power ball allocation is taken as the test point. Fig. 6. shows the measurement results of the power noise in each time domain and frequency domain. Long-term fluctuations of less than 100 MHz caused by the DC–DC converter output constant are ignored. The measured peak-to-peak power noise is up to 80 mV, and is 6.75 mV at 300 MHz in the frequency domain. The main spectrums are 300 MHz and its harmonics. Fig. 7 compares the main spectrum distribution between the simulated and measured power noise values. Compared to our previous work ⁽²⁰⁾, the proposed enhanced SCPM methodology is measured and confirmed that the frequency-domain peak harmonic voltage is improved by 28%, while the time-domain peak-to-peak voltage is improved by 6%. The standard deviation of the frequency-domain comparison in this work is 0.514, while that in ⁽²⁰⁾ is 0.867. The harmonic amplitude between the simulated and measured data has the same tendency. In the 150 MHz power noise spectrum, there is a large error between the measurement and estimation, which is due to the 150 MHz external power noise coupling in the entire TCON system.

IV. CONCLUSIONS

This paper proposes an enhanced SCPM methodology including the current slope profile information for the TCON of DTV applications. As we conclude from this experience, the proposed SCPM methodology can be applied to predict the harmonic profile of the current consumption, and is able to refine the peak amplitude of the current shape. The risk of error in the voltage noise estimation carried out during the early stage of the design process is verified using a display TCON operated with the FIFO approach.