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REFERENCES

1 
Smith L. D., Aug, Power distribution system design methodology and capacitor selection for modern CMOS technology, Advanced Packaging, IEEE Transactions on, Vol. 22, No. 3, pp. 284-291DOI
2 
Brooks D. M., Nov 2000, Power-aware micro-architecture: design and modeling challenges for next-generation microprocessors, IEEE Micro, Vol. 20, No. 6, pp. 26-44DOI
3 
Swaminathan M., Engin A. E., 2007, Power Integrity Modeling and Design for Semiconductors and Systems, Prentice-HallGoogle Search
4 
Koo K., Lee Y., Baek W., Jan 2015, Extended CPM for system power integrity analysis, Proc. IEEE Elect. Design of Adv. Packag. and Syst. Symp., Vol. , No. , pp. 217-220DOI
5 
Tanaka M. S., Oct 2011, Early stage chip/package/ board co-design techniques for system-on-chip, Proc. IEEE Conf. Elect. Perform. Electron. Packag. Syst., pp. 21-24DOI
6 
Chen H. H., Neely J. S., Aug 1998, Interconnect and circuit modeling techniques for full-chip power supply noise analysis, Components, Packaging, and Manufacturing Technology: Part B, IEEE Transactions on, Vol. 21, No. 3, pp. 209-215DOI
7 
Choi J., Oct 2005, Modeling of power supply noise in large chips using the circuit-based finite-difference time-domain method, Electromagnetic Compatibility, IEEE Transactions on, Vol. 47, No. 3, pp. 424-439DOI
8 
Lalgudi S. N., April 2008, On-chip power-grid simulation using latency insertion method, Circuits and Systems I: Regular Papers, IEEE Transactions on, Vol. 55, No. 3, pp. 914-931DOI
9 
Hu D., May 2015, System power noise analysis using modulated CPM, Proc. IEEE Symp. Electromagn. Compat. Signal Integrity, pp. 265-270DOI
10 
Kulali E., Wasserman E., Zheng J., Oct 2007, Chip power model—A new methodology for system power integrity analysis and design, Proc. IEEE Conf. Elect. Perform. Electron. Packag., pp. 259-262DOI
11 
Yang M., Oct 2013, SoC power integrity from early estimation to design signoff, Proc. IEEE Conf. Elect. Perform. Electron., pp. 3DOI
12 
Tang K. T., Friedman E. G., Aug 2002, Simultaneous switching noise in on-chip CMOS power distribution networks, Very Large Scale Integration (VLSI) System, IEEE Transactions on, Vol. 10, No. 4, pp. 487-493DOI
13 
Ko B., Sep 2016, Practical approach to power integrity-driven design process for power-delivery networks, IET Circuits Devices and Systems, Vol. 10, No. 5, pp. 448-455DOI
14 
Kim G.-W., May 2014, Package embedded decoupling capacitor impact on core power delivery network for ARM SoC application, Proc. IEEE Electron Component Technology Conf., pp. 354-359DOI
15 
Knighten J., 2005, PDN design strategies: I. ceramic SMT decoupling capacitors–what values should I choose?, IEEE EMC Society Newsletters, http://www.emcs.org/newsletters. html, Vol. 207Google Search
16 
Knighten J., 2006, PDN design strategies: II. ceramic SMT decoupling capacitors–does location matter?, IEEE EMC Society Newsletters, http://www.emcs.org/newsletters.html, Vol. 208Google Search
17 
Xing-Ming L., Jan 2014, Power distribution network design from charge delivery perspective, IEEE Electromagnetic Compatibility Magazine, Vol. 3, No. 4, pp. 55-61DOI
18 
Fizesan R., Pitica D., Sep 2010, Simulation for power integrity to design a PCB for an optimum cost, Proc. IEEE Int. Symp. Design Technol. Electron. Package, pp. 141-146DOI
19 
Jun F., Nov 2001, Quantifying SMT decoupling capacitor placement in DC power-bus design for multilayer PCBs, Electromagnetic Compatibility, IEEE Transactions on, Vol. 43, No. 4, pp. 588-599DOI
20 
Ko B., Oct 2016, Simplified chip power modeling methodology without netlist information in early stage of SoC design process, Components, Packaging and Manufacturing Technology, IEEE Transactions on, Vol. 6, No. 10, pp. 1513-1521DOI
21 
You B. H., Oct 2012, UD resolution 240Hz LCD TV display system with high speed driving, SID Symp. Dig., pp. 395-398DOI
22 
Kim S. S., July 2009, World’s first 240Hz TFT-LCD technology for full-HD LCD-TV and its application to 3D display, SID Symp. Dig., pp. 424-427Google Search
23 
Smith L., Sep 2009, System power distribution network theory and performance with various noise current stimuli including impacts on chip level timing, Proc. IEEE Custom Integrated Circuits Conf., pp. 621-628DOI
24 
Kim W., Sep 2011, Estimation of simultaneous switching noise from frequency domain impedance response of resonant power distribution networks, Components, Packaging and Manufacturing Technology, IEEE Transactions on, Vol. 1, No. 9, pp. 1359-1367DOI
25 
Tajalli A., Leblebici Y., Feb 2009, Slew controlled LVDS output driver circuit in 0.18μm CMOS technology, Solid-State Circuits, IEEE Journal of, Vol. 44, No. 2, pp. 538-548DOI
26 
Kim W., April 2001, LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS, Solid-State Cir-cuits IEEE Journal of, Vol. 36, No. 4, pp. 706-711DOI