| Title |
Common-mode Voltage Reduction of Three Level Four Leg PWM Converter |
| Authors |
Seung-Jun Chee ; Sanggi Ko ; Hyeon-Sik Kim ; Seung-Ki Sul |
| DOI |
10.6113/TKPE/2014.19.6.488 |
| Keywords |
Pulse width modulation(PWM); Sinusoidal PWM(SPWM); Space-vector PWM(SVPWM); Digital signal processor(DSP); Common-mode voltage(CMV); Common-mode current(CMC) |
| Abstract |
This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called “f leg pole voltage” is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%. |