| Title |
Parasitic Inductance Reduction Design Method of Vertical Lattice Loop Structure for Stable Driving of GaN HEMT |
| Authors |
Si-Seok Yang ; Jae-Hwan Soh ; Sung-Soo Min ; Rae-Young Kim |
| DOI |
10.6113/TKPE.2020.25.3.195 |
| Keywords |
GaN; Parasitic inductance; PCB layout; Flux cancellation |
| Abstract |
This paper presents a parasitic inductance reduction design method for the stable driving of GaN HEMT. To reduce the parasitic inductance, we propose a vertical lattice loop structure with multiple loops that is not affected by the GaN HEMT package. The proposed vertical lattice loop structure selects the reference loop and designs the same loop as the reference loop by layering. The design reverses the current direction of adjacent current paths, increasing magnetic flux cancellation to reduce parasitic inductance. In this study, we validate the effectiveness of the parasitic inductance reduction method of the proposed vertical lattice loop structure. |