| Title |
A Design Methodology of Digital Controller Considering Time Delay Effect for a Modular Multilevel Converter VSC HVDC System |
| Authors |
Ji-Wan Song ; Nam-Joon Ku ; Rae-Young Kim |
| DOI |
10.6113/TKPE/2016.21.1.49 |
| Keywords |
Time delay effect; Modular multilevel converter; Digital control; High voltage direct current |
| Abstract |
A modular multilevel converter is widely adapted for a high-voltage direct current power transmission system. This study proposes a design methodology for a novel digital control that mitigates the negative effects caused by time delay, including communication transport delay for a modular multilevel converter. The modeling and negative effect of time delay are analyzed theoretically in a frequency domain, and its compensation methodology based on an inverse model is described fully with practical considerations. The proposed methodology is verified through several simulation results using a modular 21-level converter system. |